AON_TIMER Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	542.652us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.490s	1.009ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	493.353us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	14.850s	9.605ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.600s	536.271us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.670s	517.901us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	493.353us	20	20	100.00
		aon_timer_csr_aliasing	1.600s	536.271us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.100s	373.391us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.980s	341.860us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.440m	57.685ms	50	50	100.00
V2	jump	aon_timer_jump	1.650s	599.393us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.913m	546.818ms	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.330s	510.416us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.150s	621.368us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.150s	621.368us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.490s	1.009ms	5	5	100.00
		aon_timer_csr_rw	1.350s	493.353us	20	20	100.00
		aon_timer_csr_aliasing	1.600s	536.271us	5	5	100.00
		aon_timer_same_csr_outstanding	3.790s	1.698ms	17	20	85.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.490s	1.009ms	5	5	100.00
		aon_timer_csr_rw	1.350s	493.353us	20	20	100.00
		aon_timer_csr_aliasing	1.600s	536.271us	5	5	100.00
		aon_timer_same_csr_outstanding	3.790s	1.698ms	17	20	85.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	13.890s	8.421ms	5	5	100.00
		aon_timer_tl_intg_err	13.990s	8.174ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.990s	8.174ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	18.228m	152.802ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			427	430	99.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	99.82	94.68	100.00	--	99.35	100.00	96.90

Failure Buckets

Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))' has 3 failures:

Test aon_timer_same_csr_outstanding has 3 failures.

4.aon_timer_same_csr_outstanding.834668853
Line 218, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 1723634589 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 1723634589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aon_timer_same_csr_outstanding.3461987058
Line 217, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 960479370 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 960479370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.