Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1366528265	7842940	0	0
wdog_bark_thold_rd_A	1366528265	322790	0	0
wdog_bite_thold_rd_A	1366528265	272885	0	0
wdog_ctrl_rd_A	1366528265	285120	0	0
wdog_regwen_rd_A	1366528265	310005	0	0
wkup_ctrl_rd_A	1366528265	279445	0	0
wkup_thold_rd_A	1366528265	322185	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	7842940	0	0
T1	28139	0	0	0
T2	23416	0	0	0
T3	23416	0	0	0
T6	25926	133	0	0
T7	22232	0	0	0
T8	22184	0	0	0
T9	0	2	0	0
T12	0	2	0	0
T14	22232	0	0	0
T15	25374	2	0	0
T18	0	2	0	0
T33	25374	2	0	0
T34	22184	0	0	0
T52	0	2	0	0
T53	0	133	0	0
T54	0	133	0	0
T73	0	2	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	322790	0	0
T1	28139	13	0	0
T2	23416	0	0	0
T3	23416	0	0	0
T4	28139	13	0	0
T5	0	10	0	0
T9	0	22	0	0
T10	0	10	0	0
T14	22232	0	0	0
T15	25374	7	0	0
T16	22184	0	0	0
T17	22232	0	0	0
T18	0	7	0	0
T33	25374	7	0	0
T34	22184	0	0	0
T52	0	7	0	0
T73	0	7	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	272885	0	0
T1	28139	27	0	0
T2	23416	0	0	0
T3	23416	0	0	0
T4	28139	27	0	0
T5	0	3	0	0
T9	0	30	0	0
T10	0	3	0	0
T14	22232	0	0	0
T15	25374	2	0	0
T16	22184	0	0	0
T17	22232	0	0	0
T18	0	2	0	0
T33	25374	2	0	0
T34	22184	0	0	0
T52	0	2	0	0
T73	0	2	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	285120	0	0
T1	28139	11	0	0
T2	23416	0	0	0
T3	23416	0	0	0
T4	0	11	0	0
T5	0	10	0	0
T6	25926	10	0	0
T7	22232	0	0	0
T8	22184	0	0	0
T9	0	38	0	0
T10	0	10	0	0
T14	22232	0	0	0
T15	25374	2	0	0
T18	0	2	0	0
T33	25374	2	0	0
T34	22184	0	0	0
T52	0	2	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	310005	0	0
T1	28139	35	0	0
T2	23416	6	0	0
T3	23416	6	0	0
T4	0	35	0	0
T6	25926	27	0	0
T7	22232	0	0	0
T8	22184	0	0	0
T9	0	27	0	0
T14	22232	0	0	0
T15	25374	1	0	0
T18	0	1	0	0
T33	25374	1	0	0
T34	22184	0	0	0
T52	0	1	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	279445	0	0
T1	28139	14	0	0
T2	23416	5	0	0
T3	23416	5	0	0
T4	0	14	0	0
T5	0	13	0	0
T6	25926	13	0	0
T7	22232	0	0	0
T8	22184	0	0	0
T9	0	25	0	0
T10	0	13	0	0
T11	0	5	0	0
T14	22232	0	0	0
T15	25374	0	0	0
T33	25374	0	0	0
T34	22184	0	0	0
T53	0	13	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	322185	0	0
T1	28139	37	0	0
T2	23416	0	0	0
T3	23416	0	0	0
T4	0	37	0	0
T5	0	6	0	0
T6	25926	15	0	0
T7	22232	0	0	0
T8	22184	0	0	0
T9	0	15	0	0
T10	0	6	0	0
T12	0	15	0	0
T14	22232	0	0	0
T15	25374	0	0	0
T33	25374	0	0	0
T34	22184	0	0	0
T53	0	15	0	0
T54	0	15	0	0
T55	0	15	0	0