Module Definition
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Module : aon_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 66.67 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 93.33 100.00 66.67 100.00 100.00 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 66.67 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.59 99.82 95.32 100.00 99.35 98.45


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
aon_timer_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
tlul_assert_device 99.30 100.00 100.00 97.90
u_aon_intr_flop 100.00 100.00 100.00
u_core 100.00 100.00 100.00 100.00
u_intr_hw 100.00 100.00 100.00 100.00
u_intr_sync 100.00 100.00 100.00
u_lc_sync_escalate_en 100.00 100.00 100.00 100.00
u_reg 98.96 99.80 95.72 100.00 99.30 100.00
u_sync_sleep_mode 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : aon_timer
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN20911100.00
CONT_ASSIGN21011100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN24011100.00
ALWAYS24333100.00
CONT_ASSIGN25011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
81 1 1
82 1 1
83 1 1
84 1 1
108 1 1
164 1 1
168 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 1 1
208 1 1
209 1 1
210 1 1
211 1 1
229 1 1
230 1 1
233 1 1
240 1 1
243 1 1
244 1 1
246 1 1
250 1 1

Cond Coverage for Module : aon_timer
TotalCoveredPercent
Conditions12866.67
Logical12866.67
Non-Logical00
Event00

 LINE       108
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT19,T20,T21
11Not Covered 

 LINE       164
 EXPRESSION (aon_wkup_intr_set | aon_wdog_intr_set)
             --------1--------   --------2--------
-1--2-StatusTests
00CoveredT19,T20,T21
01CoveredT28,T29,T35
10CoveredT19,T20,T21 

 LINE       200
 EXPRESSION (reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe)
             -------------------1------------------   -----------------2-----------------
-1--2-StatusTests
00CoveredT19,T20,T21
01Not Covered
10Not Covered 

 LINE       240
 EXPRESSION (aon_rst_req_set | aon_rst_req_q)
             -------1-------   ------2------
-1--2-StatusTests
00CoveredT19,T20,T21
01CoveredT20,T21,T27
10CoveredT20,T21,T27
Toggle Coverage for Module : aon_timer
TotalCoveredPercent
Totals 35 35 100.00
Total Bits 356 356 100.00
Total Bits 0->1 178 178 100.00
Total Bits 1->0 178 178 100.00

Ports 35 35 100.00
Port Bits 356 356 100.00
Port Bits 0->1 178 178 100.00
Port Bits 1->0 178 178 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
clk_aon_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_ni Yes Yes T33,T15,T9 Yes T6,T7,T8 INPUT
rst_aon_ni Yes Yes T33,T15,T9 Yes T6,T7,T8 INPUT
tl_i.d_ready Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T6,T8,T33 Yes T6,T7,T8 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T6,T8,T33 Yes T6,T8,T33 INPUT
tl_i.a_mask[3:0] Yes Yes T6,T8,T33 Yes T6,T7,T8 INPUT
tl_i.a_address[31:0] Yes Yes T6,T8,T33 Yes T6,T7,T8 INPUT
tl_i.a_source[7:0] Yes Yes T6,T8,T33 Yes T6,T8,T33 INPUT
tl_i.a_size[1:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_valid Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_o.a_ready Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
tl_o.d_error Yes Yes T6,T33,T15 Yes T6,T33,T15 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T8,T33,T34 Yes T8,T33,T34 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes T6,*T8,T33 Yes T6,T8,T33 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T8,T33 Yes T6,T8,T33 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T6,T33,T1 Yes T6,T8,T33 OUTPUT
tl_o.d_size[1:0] Yes Yes T6,T8,T33 Yes T6,T8,T33 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T6,*T8,*T33 Yes T6,T7,T8 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
alert_rx_i[0].ack_n Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T28,T29,T35 Yes T28,T29,T35 INPUT
intr_wkup_timer_expired_o Yes Yes T8,T34,T16 Yes T8,T34,T16 OUTPUT
intr_wdog_timer_bark_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
nmi_wdog_timer_bark_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
wkup_req_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
aon_timer_rst_req_o Yes Yes T20,T21,T27 Yes T1,T2,T3 OUTPUT
sleep_mode_i Yes Yes T19,T20,T21 Yes T28,T29,T35 INPUT

*Tests covering at least one bit in the range
Branch Coverage for Module : aon_timer
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 243 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	243	if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T19,T20,T21
0 Covered T19,T20,T21

Assert Coverage for Module : aon_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 1355292940 1354750280 0 0
FpvSecCmRegWeOnehotCheck_A 1355292940 50 0 0
IntrWdogKnown_A 1355292940 1354750280 0 0
IntrWkupKnown_A 1355292940 1354750280 0 0
RstReqKnown_A 4839865 4783115 0 0
TlOAReadyKnown_A 1355292940 1354750280 0 0
TlODValidKnown_A 1355292940 1354750280 0 0
WkupReqKnown_A 4839865 4783115 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355292940 1354750280 0 0
T19 26583 26530 0 0
T20 541860 540874 0 0
T21 541860 540874 0 0
T22 27505 27452 0 0
T23 27505 27452 0 0
T24 26583 26530 0 0
T25 298189 298184 0 0
T26 26583 26530 0 0
T27 541860 540874 0 0
T36 26583 26530 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355292940 50 0 0
T37 239148 10 0 0
T38 239148 10 0 0
T39 0 10 0 0
T40 0 10 0 0
T41 0 10 0 0
T42 27505 0 0 0
T43 26583 0 0 0
T44 541860 0 0 0
T45 27505 0 0 0
T46 298189 0 0 0
T47 541860 0 0 0
T48 541860 0 0 0
T49 26583 0 0 0

IntrWdogKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355292940 1354750280 0 0
T19 26583 26530 0 0
T20 541860 540874 0 0
T21 541860 540874 0 0
T22 27505 27452 0 0
T23 27505 27452 0 0
T24 26583 26530 0 0
T25 298189 298184 0 0
T26 26583 26530 0 0
T27 541860 540874 0 0
T36 26583 26530 0 0

IntrWkupKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355292940 1354750280 0 0
T19 26583 26530 0 0
T20 541860 540874 0 0
T21 541860 540874 0 0
T22 27505 27452 0 0
T23 27505 27452 0 0
T24 26583 26530 0 0
T25 298189 298184 0 0
T26 26583 26530 0 0
T27 541860 540874 0 0
T36 26583 26530 0 0

RstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4839865 4783115 0 0
T19 93 18 0 0
T20 19350 19240 0 0
T21 19350 19240 0 0
T22 97 22 0 0
T23 97 22 0 0
T24 93 18 0 0
T25 10648 10573 0 0
T26 93 18 0 0
T27 19350 19240 0 0
T36 93 18 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355292940 1354750280 0 0
T19 26583 26530 0 0
T20 541860 540874 0 0
T21 541860 540874 0 0
T22 27505 27452 0 0
T23 27505 27452 0 0
T24 26583 26530 0 0
T25 298189 298184 0 0
T26 26583 26530 0 0
T27 541860 540874 0 0
T36 26583 26530 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355292940 1354750280 0 0
T19 26583 26530 0 0
T20 541860 540874 0 0
T21 541860 540874 0 0
T22 27505 27452 0 0
T23 27505 27452 0 0
T24 26583 26530 0 0
T25 298189 298184 0 0
T26 26583 26530 0 0
T27 541860 540874 0 0
T36 26583 26530 0 0

WkupReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4839865 4783115 0 0
T19 93 18 0 0
T20 19350 19240 0 0
T21 19350 19240 0 0
T22 97 22 0 0
T23 97 22 0 0
T24 93 18 0 0
T25 10648 10573 0 0
T26 93 18 0 0
T27 19350 19240 0 0
T36 93 18 0 0

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