Unified Coverage Report :: Module :: aon_timer_reg_top

Module : aon_timer_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.52	100.00	98.08			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.52	100.00	98.08			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.52	100.00	98.08			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.96	99.80	95.72	100.00		99.30	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_intr_state_wdog_timer_bark	100.00	100.00	100.00			100.00
u_intr_state_wkup_timer_expired	100.00	100.00	100.00			100.00
u_intr_test_wdog_timer_bark	100.00	100.00
u_intr_test_wkup_timer_expired	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_wdog_bark_thold	100.00	100.00	100.00			100.00
u_wdog_bark_thold_cdc	99.17	100.00	96.67			100.00	100.00
u_wdog_bite_thold	100.00	100.00	100.00			100.00
u_wdog_bite_thold_cdc	99.17	100.00	96.67			100.00	100.00
u_wdog_count	100.00	100.00	100.00			100.00
u_wdog_count_cdc	97.11	100.00	90.14			98.31	100.00
u_wdog_ctrl_cdc	99.17	100.00	96.67			100.00	100.00
u_wdog_ctrl_enable	100.00	100.00	100.00			100.00
u_wdog_ctrl_pause_in_sleep	100.00	100.00	100.00			100.00
u_wdog_regwen	100.00	100.00	100.00			100.00
u_wkup_cause	100.00	100.00	100.00			100.00
u_wkup_cause_cdc	97.18	100.00	90.41			98.31	100.00
u_wkup_count	100.00	100.00	100.00			100.00
u_wkup_count_cdc	97.11	100.00	90.14			98.31	100.00
u_wkup_ctrl_cdc	99.17	100.00	96.67			100.00	100.00
u_wkup_ctrl_enable	100.00	100.00	100.00			100.00
u_wkup_ctrl_prescaler	100.00	100.00	100.00			100.00
u_wkup_thold	100.00	100.00	100.00			100.00
u_wkup_thold_cdc	99.17	100.00	96.67			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : aon_timer_reg_top

	Line No.	Total	Covered	Percent
TOTAL		127	127	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	177	3	3	100.00
CONT_ASSIGN	206	1	1	100.00
ALWAYS	216	2	2	100.00
CONT_ASSIGN	244	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	299	3	3	100.00
CONT_ASSIGN	328	1	1	100.00
ALWAYS	339	2	2	100.00
CONT_ASSIGN	367	1	1	100.00
ALWAYS	378	2	2	100.00
CONT_ASSIGN	406	1	1	100.00
ALWAYS	419	4	4	100.00
CONT_ASSIGN	449	1	1	100.00
ALWAYS	462	4	4	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	661	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	781	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	899	1	1	100.00
CONT_ASSIGN	904	1	1	100.00
ALWAYS	935	13	13	100.00
CONT_ASSIGN	950	1	1	100.00
ALWAYS	954	1	1	100.00
CONT_ASSIGN	970	1	1	100.00
CONT_ASSIGN	972	1	1	100.00
CONT_ASSIGN	973	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	978	1	1	100.00
CONT_ASSIGN	980	1	1	100.00
CONT_ASSIGN	982	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	996	1	1	100.00
CONT_ASSIGN	997	1	1	100.00
CONT_ASSIGN	999	1	1	100.00
CONT_ASSIGN	1001	1	1	100.00
CONT_ASSIGN	1002	1	1	100.00
ALWAYS	1007	13	13	100.00
ALWAYS	1024	16	16	100.00
CONT_ASSIGN	1080	1	1	100.00
ALWAYS	1082	10	10	100.00
CONT_ASSIGN	1121	1	1	100.00
CONT_ASSIGN	1122	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
94	1	1
95	1	1
123	1	1
124	1	1
177	1	1
178	1	1
179	1	1
206	1	1
216	1	1
217	1	1
244	1	1
257	1	1
258	1	1
259	1	1
260	1	1
287	1	1
299	1	1
300	1	1
301	1	1
328	1	1
339	1	1
340	1	1
367	1	1
378	1	1
379	1	1
406	1	1
419	1	1
420	1	1
421	1	1
422	1	1
449	1	1
462	1	1
463	1	1
464	1	1
465	1	1
492	1	1
499	1	1
513	1	1
602	1	1
661	1	1
720	1	1
751	1	1
781	1	1
868	1	1
883	1	1
899	1	1
904	1	1
935	1	1
936	1	1
937	1	1
938	1	1
939	1	1
940	1	1
941	1	1
942	1	1
943	1	1
944	1	1
945	1	1
946	1	1
947	1	1
950	1	1
954	1	1
970	1	1
972	1	1
973	1	1
976	1	1
978	1	1
980	1	1
982	1	1
983	1	1
986	1	1
988	1	1
990	1	1
992	1	1
994	1	1
996	1	1
997	1	1
999	1	1
1001	1	1
1002	1	1
1007	1	1
1008	1	1
1009	1	1
1010	1	1
1011	1	1
1012	1	1
1013	1	1
1014	1	1
1015	1	1
1016	1	1
1017	1	1
1018	1	1
1019	1	1
1024	1	1
1025	1	1
1027	1	1
1031	1	1
1034	1	1
1037	1	1
1040	1	1
1044	1	1
1047	1	1
1050	1	1
1053	1	1
1056	1	1
1057	1	1
1061	1	1
1062	1	1
1066	1	1
1080	1	1
1082	1	1
1083	1	1
1085	1	1
1088	1	1
1091	1	1
1094	1	1
1097	1	1
1100	1	1
1103	1	1
1106	1	1
1121	1	1
1122	1	1

---

Cond Coverage for Module : aon_timer_reg_top

	Total	Covered	Percent
Conditions	156	153	98.08
Logical	156	153	98.08
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T53,T54
1	1	Covered	T6,T8,T33

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T37,T38,T39
1	0	Covered	T9,T12,T72

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T6,T7,T8
0	0	1	Covered	T37,T38,T39
0	1	0	Covered	T9,T12,T72
1	0	0	Covered	T9,T12,T37

 LINE       124
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T6,T7,T8
0	0	1	Covered	T9,T12,T72
0	1	0	Covered	T6,T53,T54
1	0	0	Covered	T6,T53,T54

 LINE       124
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T9,T53

 LINE       661
 EXPRESSION (aon_wdog_ctrl_we & aon_wdog_ctrl_regwen)
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T9,T12,T19
1	1	Covered	T1,T2,T3

 LINE       720
 EXPRESSION (aon_wdog_bark_thold_we & aon_wdog_bark_thold_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T9
1	1	Covered	T2,T3,T9

 LINE       751
 EXPRESSION (aon_wdog_bite_thold_we & aon_wdog_bite_thold_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T9
1	1	Covered	T2,T3,T9

 LINE       936
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_ALERT_TEST_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T8,T33

 LINE       937
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CTRL_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T8,T33

 LINE       938
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_THOLD_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T8,T33

 LINE       939
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_COUNT_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T33,T1

 LINE       940
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T8,T33

 LINE       941
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_CTRL_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T8,T33

 LINE       942
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BARK_THOLD_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T8,T33

 LINE       943
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BITE_THOLD_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T33,T1

 LINE       944
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_COUNT_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T33,T1

 LINE       945
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_STATE_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T6,T8,T33
1	Covered	T6,T7,T8

 LINE       946
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_TEST_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T8,T33

 LINE       947
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CAUSE_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T33,T1

 LINE       950
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       950
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T8,T33
1	0	Covered	T6,T7,T8

 LINE       954
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T8,T33
1	1	Covered	T6,T9,T53

 LINE       954
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	Covered	T6,T7,T8
0	0	0	0	0	0	0	0	0	0	0	1	Covered	T6,T33,T1
0	0	0	0	0	0	0	0	0	0	1	0	Covered	T6,T8,T33
0	0	0	0	0	0	0	0	0	1	0	0	Covered	T6,T8,T33
0	0	0	0	0	0	0	0	1	0	0	0	Covered	T6,T33,T1
0	0	0	0	0	0	0	1	0	0	0	0	Covered	T6,T33,T1
0	0	0	0	0	0	1	0	0	0	0	0	Covered	T6,T8,T33
0	0	0	0	0	1	0	0	0	0	0	0	Covered	T6,T1,T2
0	0	0	0	1	0	0	0	0	0	0	0	Covered	T6,T33,T1
0	0	0	1	0	0	0	0	0	0	0	0	Covered	T6,T33,T1
0	0	1	0	0	0	0	0	0	0	0	0	Covered	T6,T8,T33
0	1	0	0	0	0	0	0	0	0	0	0	Covered	T6,T7,T8
1	0	0	0	0	0	0	0	0	0	0	0	Covered	T6,T33,T1

 LINE       954
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T33
1	0	Covered	T6,T8,T33
1	1	Covered	T6,T33,T1

 LINE       954
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T33
1	0	Covered	T6,T8,T33
1	1	Covered	T6,T7,T8

 LINE       954
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T33,T1
1	1	Covered	T6,T8,T33

 LINE       954
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T33,T1
1	1	Covered	T6,T33,T1

 LINE       954
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T33
1	0	Covered	T6,T8,T33
1	1	Covered	T6,T33,T1

 LINE       954
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T33
1	0	Covered	T6,T8,T33
1	1	Covered	T6,T1,T2

 LINE       954
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T33,T1
1	1	Covered	T6,T8,T33

 LINE       954
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T33,T1
1	1	Covered	T6,T33,T1

 LINE       954
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T33,T1
1	1	Covered	T6,T33,T1

 LINE       954
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T33
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T8,T33

 LINE       954
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T33
1	0	Covered	T6,T8,T33
1	1	Covered	T6,T8,T33

 LINE       954
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T33
1	0	Covered	T6,T33,T1
1	1	Covered	T6,T33,T1

 LINE       970
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T8,T33
1	1	0	Covered	T6,T53,T54
1	1	1	Covered	T33,T1,T2

 LINE       973
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T6,T9,T53
1	1	1	Covered	T33,T1,T2

 LINE       976
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T8,T33
1	1	0	Covered	T6,T53,T54
1	1	1	Covered	T33,T1,T2

 LINE       978
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T33,T1
1	1	0	Covered	T6,T53,T54
1	1	1	Covered	T33,T1,T2

 LINE       980
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T8,T33
1	1	0	Covered	T6,T53,T54
1	1	1	Covered	T33,T1,T2

 LINE       983
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T8,T33
1	1	0	Covered	T20,T21,T27
1	1	1	Covered	T33,T1,T2

 LINE       986
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T8,T33
1	1	0	Covered	T6,T53,T54
1	1	1	Covered	T33,T1,T2

 LINE       988
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T33,T1
1	1	0	Covered	T6,T53,T54
1	1	1	Covered	T33,T1,T2

 LINE       990
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T33,T1
1	1	0	Covered	T6,T9,T53
1	1	1	Covered	T33,T1,T2

 LINE       992
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T20,T21,T27
1	1	1	Covered	T8,T33,T34

 LINE       997
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T8,T33
1	1	0	Covered	T6,T53,T54
1	1	1	Covered	T8,T33,T34

 LINE       1002
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T34
1	0	1	Covered	T6,T33,T1
1	1	0	Covered	T6,T53,T54
1	1	1	Covered	T33,T1,T2

 LINE       1080
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T33,T1,T2

---

Branch Coverage for Module : aon_timer_reg_top

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	950	2	2	100.00
IF	73	3	3	100.00
CASE	1025	13	13	100.00
CASE	1083	9	9	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	950	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T9,T12,T37
0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	1025	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T6,T8,T33
addr_hit[1]	Covered	T6,T7,T8
addr_hit[2]	Covered	T6,T8,T33
addr_hit[3]	Covered	T6,T33,T1
addr_hit[4]	Covered	T6,T8,T33
addr_hit[5]	Covered	T6,T8,T33
addr_hit[6]	Covered	T6,T8,T33
addr_hit[7]	Covered	T6,T33,T1
addr_hit[8]	Covered	T6,T33,T1
addr_hit[9]	Covered	T6,T7,T8
addr_hit[10]	Covered	T6,T8,T33
addr_hit[11]	Covered	T6,T33,T1
default	Covered	T6,T8,T33

	LineNo.	Expression
-1-:	1083	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[1]	Covered	T6,T7,T8
addr_hit[2]	Covered	T6,T8,T33
addr_hit[3]	Covered	T6,T33,T1
addr_hit[5]	Covered	T6,T8,T33
addr_hit[6]	Covered	T6,T8,T33
addr_hit[7]	Covered	T6,T33,T1
addr_hit[8]	Covered	T6,T33,T1
addr_hit[11]	Covered	T6,T33,T1
default	Covered	T6,T7,T8

---

Assert Coverage for Module : aon_timer_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1366528265	407450	0	0
reAfterRv	1366528265	407450	0	0
rePulse	1366528265	101120	0	0
wePulse	1366528265	306330	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	407450	0	0
T1	28139	111	0	0
T2	23416	22	0	0
T3	23416	22	0	0
T6	25926	23	0	0
T7	22232	1	0	0
T8	22184	12	0	0
T14	22232	1	0	0
T15	25374	25	0	0
T33	25374	25	0	0
T34	22184	12	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	407450	0	0
T1	28139	111	0	0
T2	23416	22	0	0
T3	23416	22	0	0
T6	25926	23	0	0
T7	22232	1	0	0
T8	22184	12	0	0
T14	22232	1	0	0
T15	25374	25	0	0
T33	25374	25	0	0
T34	22184	12	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	101120	0	0
T1	28139	98	0	0
T2	23416	10	0	0
T3	23416	10	0	0
T6	25926	1	0	0
T7	22232	1	0	0
T8	22184	6	0	0
T14	22232	1	0	0
T15	25374	13	0	0
T33	25374	13	0	0
T34	22184	6	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366528265	306330	0	0
T1	28139	13	0	0
T2	23416	12	0	0
T3	23416	12	0	0
T4	0	13	0	0
T6	25926	22	0	0
T7	22232	0	0	0
T8	22184	6	0	0
T14	22232	0	0	0
T15	25374	12	0	0
T16	0	6	0	0
T33	25374	12	0	0
T34	22184	6	0	0