Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	622499273	6672543	0	0
wdog_bark_thold_rd_A	622499273	83720	0	0
wdog_bite_thold_rd_A	622499273	73328	0	0
wdog_ctrl_rd_A	622499273	74300	0	0
wdog_regwen_rd_A	622499273	84629	0	0
wkup_ctrl_rd_A	622499273	74100	0	0
wkup_thold_rd_A	622499273	85065	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622499273	6672543	0	0
T1	226249	4	0	0
T2	49184	0	0	0
T3	6417	14	0	0
T4	6695	0	0	0
T5	63268	0	0	0
T7	37447	0	0	0
T9	0	4	0	0
T10	0	7	0	0
T11	0	2	0	0
T13	20522	0	0	0
T14	4533	0	0	0
T15	32022	0	0	0
T16	21425	0	0	0
T23	0	233	0	0
T25	0	2	0	0
T45	0	359	0	0
T48	0	385	0	0
T54	0	2	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622499273	83720	0	0
T1	226249	9	0	0
T2	49184	0	0	0
T3	6417	0	0	0
T4	6695	0	0	0
T5	63268	3	0	0
T7	37447	0	0	0
T11	0	73	0	0
T13	20522	0	0	0
T14	4533	0	0	0
T15	32022	0	0	0
T16	21425	0	0	0
T27	0	10741	0	0
T34	0	3735	0	0
T51	0	8520	0	0
T57	0	10	0	0
T88	0	9693	0	0
T89	0	6197	0	0
T90	0	11121	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622499273	73328	0	0
T1	226249	27	0	0
T2	49184	0	0	0
T3	6417	0	0	0
T4	6695	0	0	0
T5	63268	2	0	0
T7	37447	0	0	0
T11	0	77	0	0
T13	20522	0	0	0
T14	4533	0	0	0
T15	32022	0	0	0
T16	21425	0	0	0
T27	0	9349	0	0
T34	0	3378	0	0
T51	0	7346	0	0
T57	0	7	0	0
T88	0	8772	0	0
T89	0	5105	0	0
T90	0	9980	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622499273	74300	0	0
T1	226249	35	0	0
T2	49184	0	0	0
T3	6417	0	0	0
T4	6695	1	0	0
T5	63268	17	0	0
T7	37447	0	0	0
T11	0	79	0	0
T13	20522	0	0	0
T14	4533	0	0	0
T15	32022	0	0	0
T16	21425	0	0	0
T27	0	9373	0	0
T34	0	3361	0	0
T51	0	7593	0	0
T88	0	9152	0	0
T89	0	5199	0	0
T90	0	9822	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622499273	84629	0	0
T1	226249	12	0	0
T2	49184	0	0	0
T3	6417	0	0	0
T4	6695	1	0	0
T5	63268	13	0	0
T7	37447	0	0	0
T11	0	67	0	0
T13	20522	0	0	0
T14	4533	0	0	0
T15	32022	0	0	0
T16	21425	0	0	0
T27	0	10298	0	0
T34	0	3814	0	0
T51	0	9043	0	0
T57	0	16	0	0
T88	0	10383	0	0
T89	0	5812	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622499273	74100	0	0
T1	226249	34	0	0
T2	49184	0	0	0
T3	6417	0	0	0
T4	6695	0	0	0
T5	63268	31	0	0
T7	37447	0	0	0
T11	0	105	0	0
T13	20522	0	0	0
T14	4533	0	0	0
T15	32022	0	0	0
T16	21425	0	0	0
T27	0	9472	0	0
T34	0	3618	0	0
T51	0	7837	0	0
T57	0	14	0	0
T88	0	8857	0	0
T89	0	5018	0	0
T90	0	9732	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622499273	85065	0	0
T1	226249	37	0	0
T2	49184	0	0	0
T3	6417	0	0	0
T4	6695	0	0	0
T5	63268	7	0	0
T7	37447	0	0	0
T11	0	77	0	0
T13	20522	0	0	0
T14	4533	0	0	0
T15	32022	0	0	0
T16	21425	0	0	0
T27	0	10852	0	0
T34	0	3989	0	0
T51	0	8698	0	0
T57	0	4	0	0
T88	0	10572	0	0
T89	0	5733	0	0
T90	0	11591	0	0