AON_TIMER Simulation Results

Wednesday December 20 2023 20:02:55 UTC

GitHub Revision: 9601d3bbdd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30104064247514112511662306974640835321092728874679524971043777466318536599043

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.410s	506.673us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.340s	1.110ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.230s	507.062us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	9.260s	11.514ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.560s	440.769us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.390s	521.094us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.230s	507.062us	20	20	100.00
		aon_timer_csr_aliasing	1.560s	440.769us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.230s	463.896us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.220s	433.310us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.085m	44.030ms	50	50	100.00
V2	jump	aon_timer_jump	1.470s	579.977us	50	50	100.00
V2	stress_all	aon_timer_stress_all	6.032m	213.654ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.370s	511.585us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.620s	490.619us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.620s	490.619us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.340s	1.110ms	5	5	100.00
		aon_timer_csr_rw	1.230s	507.062us	20	20	100.00
		aon_timer_csr_aliasing	1.560s	440.769us	5	5	100.00
		aon_timer_same_csr_outstanding	3.820s	2.081ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.340s	1.110ms	5	5	100.00
		aon_timer_csr_rw	1.230s	507.062us	20	20	100.00
		aon_timer_csr_aliasing	1.560s	440.769us	5	5	100.00
		aon_timer_same_csr_outstanding	3.820s	2.081ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	7.170s	4.356ms	5	5	100.00
		aon_timer_tl_intg_err	14.290s	8.342ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.290s	8.342ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	11.122m	86.276ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			429	430	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.61	99.82	95.32	100.00	--	99.35	100.00	97.16

Failure Buckets

• UVM_ERROR (aon_timer_scoreboard.sv:360) [scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (* [*] vs * [*]) has 1 failures:
  • Test aon_timer_stress_all has 1 failures.

    • 48.aon_timer_stress_all.59925653895192997600619925472136778485633861063767203829549300907996319719077
      Line 291, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_stress_all/latest/run.log

        UVM_ERROR @ 87014772656 ps: (aon_timer_scoreboard.sv:360) [uvm_test_top.env.scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (0x1 [1] vs 0x0 [0])
        UVM_INFO @ 87014772656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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