Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.30			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wdog_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wkup_cause_cdc	98.44	100.00	93.75			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	100.00	90.41			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_ctrl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bark_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bite_thold_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wkup_count_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wdog_count_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T10,T6,T13
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T13,T18,T23
1	1	Covered	T10,T6,T13

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.44	93.75

tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T1,T2

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T7,T1,T2
1	-	Covered	T7,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T13,T18
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T23,T24,T33
1	1	Covered	T6,T13,T18

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	34310262	0	0
DstReqKnown_A	26654128	25870544	0	0
SrcAckBusyChk_A	2147483647	38157	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34310262	0	0
T1	138016	7024	0	0
T2	6417648	222113	0	0
T3	134744	6802	0	0
T4	0	78136	0	0
T5	0	189087	0	0
T7	932992	810	0	0
T8	284240	0	0	0
T9	232280	0	0	0
T10	0	3776	0	0
T11	5692688	246626	0	0
T14	55656	0	0	0
T15	397432	0	0	0
T17	0	647	0	0
T29	0	3961	0	0
T31	336752	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654128	25870544	0	0
T1	568	128	0	0
T2	13360	496	0	0
T3	536	48	0	0
T7	1928	16	0	0
T8	568	16	0	0
T9	936	376	0	0
T11	11848	576	0	0
T14	912	392	0	0
T15	808	16	0	0
T31	664	16	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38157	0	0
T1	138016	8	0	0
T2	6417648	135	0	0
T3	134744	7	0	0
T4	932992	45	0	0
T5	1646608	102	0	0
T6	0	80	0	0
T10	0	8	0	0
T11	5692688	140	0	0
T12	0	16	0	0
T13	0	146	0	0
T14	55656	0	0	0
T15	397432	0	0	0
T16	120360	0	0	0
T17	472896	0	0	0
T18	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	138016	137288	0	0
T2	6417648	6405080	0	0
T3	134744	133984	0	0
T7	932992	930896	0	0
T8	284240	283456	0	0
T9	232280	231792	0	0
T11	5692688	5680200	0	0
T14	55656	54904	0	0
T15	397432	396968	0	0
T31	336752	336256	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	715942805	5739135	0	0
DstReqKnown_A	3331766	3233818	0	0
SrcAckBusyChk_A	715942805	6623	0	0
SrcBusyKnown_A	715942805	715181355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	5739135	0	0
T1	17252	767	0	0
T2	802206	27890	0	0
T3	16843	857	0	0
T4	0	1221	0	0
T5	0	14120	0	0
T7	116624	48	0	0
T8	35530	0	0	0
T9	29035	0	0	0
T10	0	465	0	0
T11	711586	30087	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	36	0	0
T29	0	498	0	0
T31	42094	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3331766	3233818	0	0
T1	71	16	0	0
T2	1670	62	0	0
T3	67	6	0	0
T7	241	2	0	0
T8	71	2	0	0
T9	117	47	0	0
T11	1481	72	0	0
T14	114	49	0	0
T15	101	2	0	0
T31	83	2	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	6623	0	0
T1	17252	1	0	0
T2	802206	17	0	0
T3	16843	1	0	0
T4	116624	1	0	0
T5	205826	9	0	0
T6	0	15	0	0
T10	0	1	0	0
T11	711586	17	0	0
T12	0	2	0	0
T13	0	26	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T16	15045	0	0	0
T17	59112	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	715181355	0	0
T1	17252	17161	0	0
T2	802206	800635	0	0
T3	16843	16748	0	0
T7	116624	116362	0	0
T8	35530	35432	0	0
T9	29035	28974	0	0
T11	711586	710025	0	0
T14	6957	6863	0	0
T15	49679	49621	0	0
T31	42094	42032	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	715942805	2910995	0	0
DstReqKnown_A	3331766	3233818	0	0
SrcAckBusyChk_A	715942805	3419	0	0
SrcBusyKnown_A	715942805	715181355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	2910995	0	0
T1	17252	925	0	0
T2	802206	27999	0	0
T3	16843	849	0	0
T4	0	11183	0	0
T5	0	20633	0	0
T7	116624	169	0	0
T8	35530	0	0	0
T9	29035	0	0	0
T10	0	463	0	0
T11	711586	31351	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	124	0	0
T29	0	447	0	0
T31	42094	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3331766	3233818	0	0
T1	71	16	0	0
T2	1670	62	0	0
T3	67	6	0	0
T7	241	2	0	0
T8	71	2	0	0
T9	117	47	0	0
T11	1481	72	0	0
T14	114	49	0	0
T15	101	2	0	0
T31	83	2	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	3419	0	0
T1	17252	1	0	0
T2	802206	17	0	0
T3	16843	1	0	0
T4	116624	7	0	0
T5	205826	12	0	0
T6	0	10	0	0
T10	0	1	0	0
T11	711586	18	0	0
T12	0	2	0	0
T13	0	11	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T16	15045	0	0	0
T17	59112	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	715181355	0	0
T1	17252	17161	0	0
T2	802206	800635	0	0
T3	16843	16748	0	0
T7	116624	116362	0	0
T8	35530	35432	0	0
T9	29035	28974	0	0
T11	711586	710025	0	0
T14	6957	6863	0	0
T15	49679	49621	0	0
T31	42094	42032	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	715942805	5055768	0	0
DstReqKnown_A	3331766	3233818	0	0
SrcAckBusyChk_A	715942805	5775	0	0
SrcBusyKnown_A	715942805	715181355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	5055768	0	0
T1	17252	755	0	0
T2	802206	26074	0	0
T3	16843	978	0	0
T4	0	16544	0	0
T5	0	21283	0	0
T7	116624	146	0	0
T8	35530	0	0	0
T9	29035	0	0	0
T10	0	481	0	0
T11	711586	31209	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	123	0	0
T29	0	511	0	0
T31	42094	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3331766	3233818	0	0
T1	71	16	0	0
T2	1670	62	0	0
T3	67	6	0	0
T7	241	2	0	0
T8	71	2	0	0
T9	117	47	0	0
T11	1481	72	0	0
T14	114	49	0	0
T15	101	2	0	0
T31	83	2	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	5775	0	0
T1	17252	1	0	0
T2	802206	16	0	0
T3	16843	1	0	0
T4	116624	10	0	0
T5	205826	13	0	0
T6	0	14	0	0
T10	0	1	0	0
T11	711586	18	0	0
T12	0	2	0	0
T13	0	22	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T16	15045	0	0	0
T17	59112	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	715181355	0	0
T1	17252	17161	0	0
T2	802206	800635	0	0
T3	16843	16748	0	0
T7	116624	116362	0	0
T8	35530	35432	0	0
T9	29035	28974	0	0
T11	711586	710025	0	0
T14	6957	6863	0	0
T15	49679	49621	0	0
T31	42094	42032	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	715942805	2933140	0	0
DstReqKnown_A	3331766	3233818	0	0
SrcAckBusyChk_A	715942805	3449	0	0
SrcBusyKnown_A	715942805	715181355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	2933140	0	0
T1	17252	891	0	0
T2	802206	27888	0	0
T3	16843	780	0	0
T4	0	14492	0	0
T5	0	24643	0	0
T7	116624	64	0	0
T8	35530	0	0	0
T9	29035	0	0	0
T10	0	469	0	0
T11	711586	31567	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	37	0	0
T29	0	491	0	0
T31	42094	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3331766	3233818	0	0
T1	71	16	0	0
T2	1670	62	0	0
T3	67	6	0	0
T7	241	2	0	0
T8	71	2	0	0
T9	117	47	0	0
T11	1481	72	0	0
T14	114	49	0	0
T15	101	2	0	0
T31	83	2	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	3449	0	0
T1	17252	1	0	0
T2	802206	17	0	0
T3	16843	1	0	0
T4	116624	9	0	0
T5	205826	15	0	0
T6	0	9	0	0
T10	0	1	0	0
T11	711586	18	0	0
T12	0	2	0	0
T13	0	11	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T16	15045	0	0	0
T17	59112	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	715181355	0	0
T1	17252	17161	0	0
T2	802206	800635	0	0
T3	16843	16748	0	0
T7	116624	116362	0	0
T8	35530	35432	0	0
T9	29035	28974	0	0
T11	711586	710025	0	0
T14	6957	6863	0	0
T15	49679	49621	0	0
T31	42094	42032	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T11
1	1	Covered	T7,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T1,T2,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	715942805	2930236	0	0
DstReqKnown_A	3331766	3233818	0	0
SrcAckBusyChk_A	715942805	3442	0	0
SrcBusyKnown_A	715942805	715181355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	2930236	0	0
T1	17252	958	0	0
T2	802206	27969	0	0
T3	16843	751	0	0
T4	0	9732	0	0
T5	0	9727	0	0
T7	116624	179	0	0
T8	35530	0	0	0
T9	29035	0	0	0
T10	0	479	0	0
T11	711586	31541	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	32	0	0
T29	0	478	0	0
T31	42094	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3331766	3233818	0	0
T1	71	16	0	0
T2	1670	62	0	0
T3	67	6	0	0
T7	241	2	0	0
T8	71	2	0	0
T9	117	47	0	0
T11	1481	72	0	0
T14	114	49	0	0
T15	101	2	0	0
T31	83	2	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	3442	0	0
T1	17252	1	0	0
T2	802206	17	0	0
T3	16843	0	0	0
T4	116624	6	0	0
T5	205826	6	0	0
T6	0	9	0	0
T10	0	1	0	0
T11	711586	18	0	0
T12	0	2	0	0
T13	0	11	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T16	15045	0	0	0
T17	59112	0	0	0
T18	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	715181355	0	0
T1	17252	17161	0	0
T2	802206	800635	0	0
T3	16843	16748	0	0
T7	116624	116362	0	0
T8	35530	35432	0	0
T9	29035	28974	0	0
T11	711586	710025	0	0
T14	6957	6863	0	0
T15	49679	49621	0	0
T31	42094	42032	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T13,T19,T20
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T13,T18,T23
1	1	Covered	T13,T19,T20

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	715942805	6249039	0	0
DstReqKnown_A	3331766	3233818	0	0
SrcAckBusyChk_A	715942805	6292	0	0
SrcBusyKnown_A	715942805	715181355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	6249039	0	0
T1	17252	951	0	0
T2	802206	28184	0	0
T3	16843	863	0	0
T4	0	10278	0	0
T5	0	51349	0	0
T7	116624	58	0	0
T8	35530	0	0	0
T9	29035	0	0	0
T10	0	475	0	0
T11	711586	31492	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	115	0	0
T29	0	540	0	0
T31	42094	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3331766	3233818	0	0
T1	71	16	0	0
T2	1670	62	0	0
T3	67	6	0	0
T7	241	2	0	0
T8	71	2	0	0
T9	117	47	0	0
T11	1481	72	0	0
T14	114	49	0	0
T15	101	2	0	0
T31	83	2	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	6292	0	0
T1	17252	1	0	0
T2	802206	17	0	0
T3	16843	1	0	0
T4	116624	5	0	0
T5	205826	24	0	0
T6	0	10	0	0
T10	0	1	0	0
T11	711586	18	0	0
T12	0	2	0	0
T13	0	27	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T16	15045	0	0	0
T17	59112	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	715181355	0	0
T1	17252	17161	0	0
T2	802206	800635	0	0
T3	16843	16748	0	0
T7	116624	116362	0	0
T8	35530	35432	0	0
T9	29035	28974	0	0
T11	711586	710025	0	0
T14	6957	6863	0	0
T15	49679	49621	0	0
T31	42094	42032	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T10,T6,T24
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T18,T23,T24
1	1	Covered	T10,T6,T24

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	715942805	5868238	0	0
DstReqKnown_A	3331766	3233818	0	0
SrcAckBusyChk_A	715942805	6341	0	0
SrcBusyKnown_A	715942805	715181355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	5868238	0	0
T1	17252	886	0	0
T2	802206	27921	0	0
T3	16843	928	0	0
T4	0	6856	0	0
T5	0	35706	0	0
T7	116624	48	0	0
T8	35530	0	0	0
T9	29035	0	0	0
T10	0	471	0	0
T11	711586	29762	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	83	0	0
T29	0	478	0	0
T31	42094	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3331766	3233818	0	0
T1	71	16	0	0
T2	1670	62	0	0
T3	67	6	0	0
T7	241	2	0	0
T8	71	2	0	0
T9	117	47	0	0
T11	1481	72	0	0
T14	114	49	0	0
T15	101	2	0	0
T31	83	2	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	6341	0	0
T1	17252	1	0	0
T2	802206	17	0	0
T3	16843	1	0	0
T4	116624	3	0	0
T5	205826	17	0	0
T6	0	9	0	0
T10	0	1	0	0
T11	711586	17	0	0
T12	0	2	0	0
T13	0	27	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T16	15045	0	0	0
T17	59112	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	715181355	0	0
T1	17252	17161	0	0
T2	802206	800635	0	0
T3	16843	16748	0	0
T7	116624	116362	0	0
T8	35530	35432	0	0
T9	29035	28974	0	0
T11	711586	710025	0	0
T14	6957	6863	0	0
T15	49679	49621	0	0
T31	42094	42032	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T1,T2

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T7,T1,T2
1	-	Covered	T7,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T13,T18
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T23,T24,T33
1	1	Covered	T6,T13,T18

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T7,T1,T2
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	715942805	2623711	0	0
DstReqKnown_A	3331766	3233818	0	0
SrcAckBusyChk_A	715942805	2816	0	0
SrcBusyKnown_A	715942805	715181355	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	2623711	0	0
T1	17252	891	0	0
T2	802206	28188	0	0
T3	16843	796	0	0
T4	0	7830	0	0
T5	0	11626	0	0
T7	116624	98	0	0
T8	35530	0	0	0
T9	29035	0	0	0
T10	0	473	0	0
T11	711586	29617	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	97	0	0
T29	0	518	0	0
T31	42094	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3331766	3233818	0	0
T1	71	16	0	0
T2	1670	62	0	0
T3	67	6	0	0
T7	241	2	0	0
T8	71	2	0	0
T9	117	47	0	0
T11	1481	72	0	0
T14	114	49	0	0
T15	101	2	0	0
T31	83	2	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	2816	0	0
T1	17252	1	0	0
T2	802206	17	0	0
T3	16843	1	0	0
T4	116624	4	0	0
T5	205826	6	0	0
T6	0	4	0	0
T10	0	1	0	0
T11	711586	16	0	0
T12	0	2	0	0
T13	0	11	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T16	15045	0	0	0
T17	59112	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	715181355	0	0
T1	17252	17161	0	0
T2	802206	800635	0	0
T3	16843	16748	0	0
T7	116624	116362	0	0
T8	35530	35432	0	0
T9	29035	28974	0	0
T11	711586	710025	0	0
T14	6957	6863	0	0
T15	49679	49621	0	0
T31	42094	42032	0	0