Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wkup_thold_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wkup_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wkup_count_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_ctrl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_thold_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wkup_count_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00	92.86			100.00	100.00	u_wkup_count_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wdog_ctrl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wdog_bark_thold_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wdog_bite_thold_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00	92.86			100.00	100.00	u_wdog_count_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.44	100.00	93.75			100.00	100.00	u_wkup_cause_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T17
1	0	Covered	T8,T1,T17
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	64615	0	0
SrcPulseCheck_M	2147483647	66797	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	64615	0	0
T1	506449	232	0	0
T2	2032485	119	0	0
T3	1141608	47	0	0
T4	0	55	0	0
T5	0	26	0	0
T6	0	122	0	0
T9	1150621	79	0	0
T10	0	12	0	0
T11	0	90	0	0
T12	0	14	0	0
T13	0	14	0	0
T14	50548	0	0	0
T15	236671	0	0	0
T16	17900	0	0	0
T17	583546	0	0	0
T18	121803	0	0	0
T19	273396	0	0	0
T20	0	3	0	0
T21	0	23	0	0
T45	0	640	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	66797	0	0
T1	797503	260	0	0
T2	3239379	243	0	0
T3	1819506	124	0	0
T4	0	56	0	0
T5	0	10	0	0
T6	0	42	0	0
T8	342328	8	0	0
T9	4660	112	0	0
T10	0	5	0	0
T11	0	90	0	0
T14	80206	0	0	0
T15	377917	0	0	0
T16	27977	0	0	0
T17	931669	16	0	0
T18	193395	0	0	0
T19	436560	16	0	0
T28	0	16	0	0
T44	0	8	0	0
T45	0	320	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T17
1	0	Covered	T8,T1,T17
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	3670851	7012	0	0
SrcPulseCheck_M	856123872	7280	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	7012	0	0
T1	1643	18	0	0
T2	1615	4	0	0
T3	906	0	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	7	0	0
T9	932	3	0	0
T10	0	1	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	7280	0	0
T1	98661	20	0	0
T2	403913	20	0	0
T3	226872	10	0	0
T4	0	4	0	0
T8	42791	1	0	0
T9	0	8	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	2	0	0
T18	24055	0	0	0
T19	54500	2	0	0
T28	0	2	0	0
T44	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	856123872	7222	0	0
SrcPulseCheck_M	3670851	7223	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	7222	0	0
T1	98661	20	0	0
T2	403913	18	0	0
T3	226872	9	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	7	0	0
T9	228633	6	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	7223	0	0
T1	1643	20	0	0
T2	1615	18	0	0
T3	906	9	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	7	0	0
T9	932	6	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T17
1	0	Covered	T8,T1,T17
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	3670851	3546	0	0
SrcPulseCheck_M	856123872	3825	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3546	0	0
T1	1643	14	0	0
T2	1615	4	0	0
T3	906	0	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	5	0	0
T9	932	6	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3825	0	0
T1	98661	20	0	0
T2	403913	20	0	0
T3	226872	10	0	0
T4	0	4	0	0
T8	42791	1	0	0
T9	0	10	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	2	0	0
T18	24055	0	0	0
T19	54500	2	0	0
T28	0	2	0	0
T44	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	856123872	3758	0	0
SrcPulseCheck_M	3670851	3759	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3758	0	0
T1	98661	20	0	0
T2	403913	18	0	0
T3	226872	9	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	5	0	0
T9	228633	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3759	0	0
T1	1643	20	0	0
T2	1615	18	0	0
T3	906	9	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	5	0	0
T9	932	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T17
1	0	Covered	T8,T1,T17
1	1	Covered	T4,T6,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	3670851	6615	0	0
SrcPulseCheck_M	856123872	6896	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	6615	0	0
T1	1643	15	0	0
T2	1615	6	0	0
T3	906	2	0	0
T4	0	8	0	0
T5	0	2	0	0
T6	0	8	0	0
T9	932	5	0	0
T10	0	1	0	0
T12	0	3	0	0
T13	0	3	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6896	0	0
T1	98661	20	0	0
T2	403913	19	0	0
T3	226872	9	0	0
T4	0	8	0	0
T8	42791	1	0	0
T9	0	9	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	2	0	0
T18	24055	0	0	0
T19	54500	2	0	0
T28	0	2	0	0
T44	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T17
1	0	Covered	T8,T1,T17
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	3670851	6058	0	0
SrcPulseCheck_M	856123872	6334	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	6058	0	0
T1	1643	17	0	0
T2	1615	4	0	0
T3	906	0	0	0
T4	0	3	0	0
T5	0	2	0	0
T6	0	9	0	0
T9	932	6	0	0
T10	0	1	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6334	0	0
T1	98661	20	0	0
T2	403913	20	0	0
T3	226872	10	0	0
T4	0	3	0	0
T8	42791	1	0	0
T9	0	10	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	2	0	0
T18	24055	0	0	0
T19	54500	2	0	0
T28	0	2	0	0
T44	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	856123872	6276	0	0
SrcPulseCheck_M	3670851	6277	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6276	0	0
T1	98661	20	0	0
T2	403913	18	0	0
T3	226872	9	0	0
T4	0	3	0	0
T5	0	2	0	0
T6	0	9	0	0
T9	228633	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	6277	0	0
T1	1643	20	0	0
T2	1615	18	0	0
T3	906	9	0	0
T4	0	3	0	0
T5	0	2	0	0
T6	0	9	0	0
T9	932	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T17
1	0	Covered	T8,T1,T17
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	3670851	3538	0	0
SrcPulseCheck_M	856123872	3814	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3538	0	0
T1	1643	17	0	0
T2	1615	4	0	0
T3	906	0	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	8	0	0
T9	932	5	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3814	0	0
T1	98661	20	0	0
T2	403913	20	0	0
T3	226872	10	0	0
T4	0	4	0	0
T8	42791	1	0	0
T9	0	9	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	2	0	0
T18	24055	0	0	0
T19	54500	2	0	0
T28	0	2	0	0
T44	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	856123872	3751	0	0
SrcPulseCheck_M	3670851	3752	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3751	0	0
T1	98661	20	0	0
T2	403913	18	0	0
T3	226872	9	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	8	0	0
T9	228633	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3752	0	0
T1	1643	20	0	0
T2	1615	18	0	0
T3	906	9	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	8	0	0
T9	932	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T17
1	0	Covered	T8,T1,T17
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	3670851	3558	0	0
SrcPulseCheck_M	856123872	3825	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3558	0	0
T1	1643	16	0	0
T2	1615	3	0	0
T3	906	0	0	0
T4	0	5	0	0
T5	0	2	0	0
T6	0	13	0	0
T9	932	5	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3825	0	0
T1	98661	20	0	0
T2	403913	18	0	0
T3	226872	10	0	0
T4	0	5	0	0
T8	42791	1	0	0
T9	0	9	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	2	0	0
T18	24055	0	0	0
T19	54500	2	0	0
T28	0	2	0	0
T44	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T4,T45,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T45,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	856123872	3769	0	0
SrcPulseCheck_M	3670851	3771	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3769	0	0
T1	98661	20	0	0
T2	403913	16	0	0
T3	226872	9	0	0
T4	0	5	0	0
T5	0	2	0	0
T6	0	13	0	0
T9	228633	7	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3771	0	0
T1	1643	20	0	0
T2	1615	16	0	0
T3	906	9	0	0
T4	0	5	0	0
T5	0	2	0	0
T6	0	13	0	0
T9	932	7	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T45	0	64	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T17
1	0	Covered	T8,T1,T17
1	1	Covered	T4,T6,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	3670851	6639	0	0
SrcPulseCheck_M	856123872	6914	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	6639	0	0
T1	1643	17	0	0
T2	1615	3	0	0
T3	906	0	0	0
T4	0	6	0	0
T5	0	2	0	0
T6	0	12	0	0
T9	932	6	0	0
T10	0	1	0	0
T12	0	3	0	0
T13	0	3	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T20	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6914	0	0
T1	98661	20	0	0
T2	403913	19	0	0
T3	226872	10	0	0
T4	0	6	0	0
T8	42791	1	0	0
T9	0	10	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	2	0	0
T18	24055	0	0	0
T19	54500	2	0	0
T28	0	2	0	0
T44	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T17
1	0	Covered	T8,T1,T17
1	1	Covered	T4,T6,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	3670851	2873	0	0
SrcPulseCheck_M	856123872	3127	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	2873	0	0
T1	1643	18	0	0
T2	1615	3	0	0
T3	906	0	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	18	0	0
T9	932	6	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	86	0	0	0
T15	97	0	0	0
T16	85	0	0	0
T17	257	0	0	0
T18	191	0	0	0
T19	112	0	0	0
T20	0	1	0	0
T21	0	23	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3127	0	0
T1	98661	20	0	0
T2	403913	19	0	0
T3	226872	10	0	0
T4	0	2	0	0
T8	42791	1	0	0
T9	0	10	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	2	0	0
T18	24055	0	0	0
T19	54500	2	0	0
T28	0	2	0	0
T44	0	1	0	0