Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.30			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wdog_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wkup_cause_cdc	98.44	100.00	93.75			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	100.00	90.41			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_ctrl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bark_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bite_thold_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wkup_count_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wdog_count_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T5,T13,T20
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T12,T21,T22
1	1	Covered	T5,T13,T20

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.44	93.75

tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T1,T19
1	-	Covered	T1,T17,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T21,T33,T43
1	1	Covered	T5,T12,T13

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	40791524	0	0
DstReqKnown_A	29366808	28600368	0	0
SrcAckBusyChk_A	2147483647	41441	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40791524	0	0
T1	789288	30173	0	0
T2	3231304	121330	0	0
T3	1814976	65030	0	0
T4	0	56544	0	0
T8	342328	1568	0	0
T9	0	52683	0	0
T14	79776	0	0	0
T15	377432	0	0	0
T16	27552	0	0	0
T17	930384	641	0	0
T18	192440	0	0	0
T19	436000	14282	0	0
T28	0	418	0	0
T44	0	2457	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29366808	28600368	0	0
T1	13144	928	0	0
T2	12920	560	0	0
T7	560	16	0	0
T8	704	16	0	0
T14	688	56	0	0
T15	776	16	0	0
T16	680	104	0	0
T17	2056	16	0	0
T18	1528	832	0	0
T19	896	48	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41441	0	0
T1	789288	158	0	0
T2	3231304	136	0	0
T3	1814976	70	0	0
T4	0	35	0	0
T5	0	16	0	0
T6	0	80	0	0
T9	1829064	60	0	0
T10	0	7	0	0
T11	0	144	0	0
T12	0	6	0	0
T13	0	1	0	0
T14	79776	0	0	0
T15	377432	0	0	0
T16	27552	0	0	0
T17	930384	0	0	0
T18	192440	0	0	0
T19	436000	0	0	0
T45	0	320	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	789288	776288	0	0
T2	3231304	3218680	0	0
T7	285000	284296	0	0
T8	342328	310880	0	0
T14	79776	79216	0	0
T15	377432	376856	0	0
T16	27552	27088	0	0
T17	930384	928688	0	0
T18	192440	191832	0	0
T19	436000	366240	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856123872	6903287	0	0
DstReqKnown_A	3670851	3575046	0	0
SrcAckBusyChk_A	856123872	7222	0	0
SrcBusyKnown_A	856123872	855363730	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6903287	0	0
T1	98661	3657	0	0
T2	403913	15763	0	0
T3	226872	8181	0	0
T4	0	5680	0	0
T8	42791	198	0	0
T9	0	5483	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	90	0	0
T18	24055	0	0	0
T19	54500	1808	0	0
T28	0	59	0	0
T44	0	306	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3575046	0	0
T1	1643	116	0	0
T2	1615	70	0	0
T7	70	2	0	0
T8	88	2	0	0
T14	86	7	0	0
T15	97	2	0	0
T16	85	13	0	0
T17	257	2	0	0
T18	191	104	0	0
T19	112	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	7222	0	0
T1	98661	20	0	0
T2	403913	18	0	0
T3	226872	9	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	7	0	0
T9	228633	6	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	855363730	0	0
T1	98661	97036	0	0
T2	403913	402335	0	0
T7	35625	35537	0	0
T8	42791	38860	0	0
T14	9972	9902	0	0
T15	47179	47107	0	0
T16	3444	3386	0	0
T17	116298	116086	0	0
T18	24055	23979	0	0
T19	54500	45780	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856123872	3581723	0	0
DstReqKnown_A	3670851	3575046	0	0
SrcAckBusyChk_A	856123872	3758	0	0
SrcBusyKnown_A	856123872	855363730	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3581723	0	0
T1	98661	3826	0	0
T2	403913	15750	0	0
T3	226872	8192	0	0
T4	0	5683	0	0
T8	42791	188	0	0
T9	0	6956	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	99	0	0
T18	24055	0	0	0
T19	54500	1774	0	0
T28	0	90	0	0
T44	0	308	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3575046	0	0
T1	1643	116	0	0
T2	1615	70	0	0
T7	70	2	0	0
T8	88	2	0	0
T14	86	7	0	0
T15	97	2	0	0
T16	85	13	0	0
T17	257	2	0	0
T18	191	104	0	0
T19	112	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3758	0	0
T1	98661	20	0	0
T2	403913	18	0	0
T3	226872	9	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	5	0	0
T9	228633	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	855363730	0	0
T1	98661	97036	0	0
T2	403913	402335	0	0
T7	35625	35537	0	0
T8	42791	38860	0	0
T14	9972	9902	0	0
T15	47179	47107	0	0
T16	3444	3386	0	0
T17	116298	116086	0	0
T18	24055	23979	0	0
T19	54500	45780	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856123872	6108294	0	0
DstReqKnown_A	3670851	3575046	0	0
SrcAckBusyChk_A	856123872	6276	0	0
SrcBusyKnown_A	856123872	855363730	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6108294	0	0
T1	98661	3861	0	0
T2	403913	15800	0	0
T3	226872	8170	0	0
T4	0	4256	0	0
T8	42791	202	0	0
T9	0	6919	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	65	0	0
T18	24055	0	0	0
T19	54500	1775	0	0
T28	0	61	0	0
T44	0	296	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3575046	0	0
T1	1643	116	0	0
T2	1615	70	0	0
T7	70	2	0	0
T8	88	2	0	0
T14	86	7	0	0
T15	97	2	0	0
T16	85	13	0	0
T17	257	2	0	0
T18	191	104	0	0
T19	112	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6276	0	0
T1	98661	20	0	0
T2	403913	18	0	0
T3	226872	9	0	0
T4	0	3	0	0
T5	0	2	0	0
T6	0	9	0	0
T9	228633	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	855363730	0	0
T1	98661	97036	0	0
T2	403913	402335	0	0
T7	35625	35537	0	0
T8	42791	38860	0	0
T14	9972	9902	0	0
T15	47179	47107	0	0
T16	3444	3386	0	0
T17	116298	116086	0	0
T18	24055	23979	0	0
T19	54500	45780	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856123872	3568660	0	0
DstReqKnown_A	3670851	3575046	0	0
SrcAckBusyChk_A	856123872	3751	0	0
SrcBusyKnown_A	856123872	855363730	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3568660	0	0
T1	98661	3871	0	0
T2	403913	15832	0	0
T3	226872	8161	0	0
T4	0	5670	0	0
T8	42791	204	0	0
T9	0	6960	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	76	0	0
T18	24055	0	0	0
T19	54500	1769	0	0
T28	0	66	0	0
T44	0	319	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3575046	0	0
T1	1643	116	0	0
T2	1615	70	0	0
T7	70	2	0	0
T8	88	2	0	0
T14	86	7	0	0
T15	97	2	0	0
T16	85	13	0	0
T17	257	2	0	0
T18	191	104	0	0
T19	112	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3751	0	0
T1	98661	20	0	0
T2	403913	18	0	0
T3	226872	9	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	8	0	0
T9	228633	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	855363730	0	0
T1	98661	97036	0	0
T2	403913	402335	0	0
T7	35625	35537	0	0
T8	42791	38860	0	0
T14	9972	9902	0	0
T15	47179	47107	0	0
T16	3444	3386	0	0
T17	116298	116086	0	0
T18	24055	23979	0	0
T19	54500	45780	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856123872	3581705	0	0
DstReqKnown_A	3670851	3575046	0	0
SrcAckBusyChk_A	856123872	3769	0	0
SrcBusyKnown_A	856123872	855363730	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3581705	0	0
T1	98661	3745	0	0
T2	403913	14064	0	0
T3	226872	8180	0	0
T4	0	7100	0	0
T8	42791	194	0	0
T9	0	6219	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	58	0	0
T18	24055	0	0	0
T19	54500	1772	0	0
T28	0	47	0	0
T44	0	313	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3575046	0	0
T1	1643	116	0	0
T2	1615	70	0	0
T7	70	2	0	0
T8	88	2	0	0
T14	86	7	0	0
T15	97	2	0	0
T16	85	13	0	0
T17	257	2	0	0
T18	191	104	0	0
T19	112	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3769	0	0
T1	98661	20	0	0
T2	403913	16	0	0
T3	226872	9	0	0
T4	0	5	0	0
T5	0	2	0	0
T6	0	13	0	0
T9	228633	7	0	0
T10	0	1	0	0
T11	0	18	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0
T45	0	64	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	855363730	0	0
T1	98661	97036	0	0
T2	403913	402335	0	0
T7	35625	35537	0	0
T8	42791	38860	0	0
T14	9972	9902	0	0
T15	47179	47107	0	0
T16	3444	3386	0	0
T17	116298	116086	0	0
T18	24055	23979	0	0
T19	54500	45780	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T13,T20,T21
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T12,T21,T22
1	1	Covered	T13,T20,T21

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856123872	7138107	0	0
DstReqKnown_A	3670851	3575046	0	0
SrcAckBusyChk_A	856123872	6780	0	0
SrcBusyKnown_A	856123872	855363730	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	7138107	0	0
T1	98661	3793	0	0
T2	403913	14572	0	0
T3	226872	7800	0	0
T4	0	14675	0	0
T8	42791	192	0	0
T9	0	6224	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	98	0	0
T18	24055	0	0	0
T19	54500	1781	0	0
T28	0	9	0	0
T44	0	298	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3575046	0	0
T1	1643	116	0	0
T2	1615	70	0	0
T7	70	2	0	0
T8	88	2	0	0
T14	86	7	0	0
T15	97	2	0	0
T16	85	13	0	0
T17	257	2	0	0
T18	191	104	0	0
T19	112	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6780	0	0
T1	98661	20	0	0
T2	403913	14	0	0
T3	226872	7	0	0
T4	0	8	0	0
T5	0	2	0	0
T6	0	8	0	0
T9	228633	7	0	0
T10	0	1	0	0
T11	0	18	0	0
T12	0	2	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	855363730	0	0
T1	98661	97036	0	0
T2	403913	402335	0	0
T7	35625	35537	0	0
T8	42791	38860	0	0
T14	9972	9902	0	0
T15	47179	47107	0	0
T16	3444	3386	0	0
T17	116298	116086	0	0
T18	24055	23979	0	0
T19	54500	45780	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T5,T21,T22
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T21,T22,T24
1	1	Covered	T5,T21,T22

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856123872	6780779	0	0
DstReqKnown_A	3670851	3575046	0	0
SrcAckBusyChk_A	856123872	6817	0	0
SrcBusyKnown_A	856123872	855363730	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6780779	0	0
T1	98661	3769	0	0
T2	403913	14766	0	0
T3	226872	8178	0	0
T4	0	10869	0	0
T8	42791	200	0	0
T9	0	6967	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	87	0	0
T18	24055	0	0	0
T19	54500	1805	0	0
T28	0	81	0	0
T44	0	315	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3575046	0	0
T1	1643	116	0	0
T2	1615	70	0	0
T7	70	2	0	0
T8	88	2	0	0
T14	86	7	0	0
T15	97	2	0	0
T16	85	13	0	0
T17	257	2	0	0
T18	191	104	0	0
T19	112	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	6817	0	0
T1	98661	19	0	0
T2	403913	17	0	0
T3	226872	9	0	0
T4	0	6	0	0
T5	0	2	0	0
T6	0	12	0	0
T9	228633	8	0	0
T10	0	1	0	0
T11	0	18	0	0
T12	0	3	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	855363730	0	0
T1	98661	97036	0	0
T2	403913	402335	0	0
T7	35625	35537	0	0
T8	42791	38860	0	0
T14	9972	9902	0	0
T15	47179	47107	0	0
T16	3444	3386	0	0
T17	116298	116086	0	0
T18	24055	23979	0	0
T19	54500	45780	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Unreachable
1	0	Covered	T8,T1,T17

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T1,T17

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T1,T19
1	-	Covered	T1,T17,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T17
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T1
1	0	Covered	T21,T33,T43
1	1	Covered	T5,T12,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T1
0	1	-	Covered	T8,T1,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856123872	3128969	0	0
DstReqKnown_A	3670851	3575046	0	0
SrcAckBusyChk_A	856123872	3068	0	0
SrcBusyKnown_A	856123872	855363730	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3128969	0	0
T1	98661	3651	0	0
T2	403913	14783	0	0
T3	226872	8168	0	0
T4	0	2611	0	0
T8	42791	190	0	0
T9	0	6955	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	68	0	0
T18	24055	0	0	0
T19	54500	1798	0	0
T28	0	5	0	0
T44	0	302	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670851	3575046	0	0
T1	1643	116	0	0
T2	1615	70	0	0
T7	70	2	0	0
T8	88	2	0	0
T14	86	7	0	0
T15	97	2	0	0
T16	85	13	0	0
T17	257	2	0	0
T18	191	104	0	0
T19	112	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	3068	0	0
T1	98661	19	0	0
T2	403913	17	0	0
T3	226872	9	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	18	0	0
T9	228633	8	0	0
T11	0	18	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	0	0	0
T19	54500	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	855363730	0	0
T1	98661	97036	0	0
T2	403913	402335	0	0
T7	35625	35537	0	0
T8	42791	38860	0	0
T14	9972	9902	0	0
T15	47179	47107	0	0
T16	3444	3386	0	0
T17	116298	116086	0	0
T18	24055	23979	0	0
T19	54500	45780	0	0