Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.30			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wdog_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wkup_cause_cdc	98.44	100.00	93.75			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	100.00	90.41			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_ctrl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bark_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bite_thold_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wkup_count_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wdog_count_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T9,T21,T22
1	1	Covered	T5,T10,T12

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.44	93.75

tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T2,T3,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T12,T30,T51
1	1	Covered	T12,T20,T23

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	35168022	0	0
DstReqKnown_A	30992688	30209752	0	0
SrcAckBusyChk_A	2147483647	38505	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35168022	0	0
T1	100527	2094	0	0
T2	6145992	257538	0	0
T3	1021576	114975	0	0
T4	0	44926	0	0
T6	118909	0	0	0
T7	141616	4459	0	0
T8	0	60290	0	0
T9	0	2788	0	0
T13	1232696	135364	0	0
T14	90080	0	0	0
T15	45216	0	0	0
T16	225424	0	0	0
T17	470016	12520	0	0
T52	122234	723	0	0
T53	0	384	0	0
T54	0	90	0	0
T55	23839	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30992688	30209752	0	0
T1	944	104	0	0
T2	13208	584	0	0
T3	3392	2648	0	0
T6	528	24	0	0
T7	576	64	0	0
T13	9848	9208	0	0
T14	712	56	0	0
T15	888	104	0	0
T16	464	16	0	0
T17	960	48	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38505	0	0
T1	100527	7	0	0
T2	6145992	160	0	0
T3	1021576	99	0	0
T4	0	89	0	0
T5	0	50	0	0
T6	118909	0	0	0
T7	141616	7	0	0
T8	0	142	0	0
T9	0	158	0	0
T10	0	8	0	0
T11	0	18	0	0
T12	0	2	0	0
T13	1232696	320	0	0
T14	90080	0	0	0
T15	45216	0	0	0
T16	225424	0	0	0
T17	470016	0	0	0
T52	122234	0	0	0
T55	23839	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	114888	108696	0	0
T2	6145992	6133664	0	0
T3	1021576	1020952	0	0
T6	135896	135224	0	0
T7	141616	121640	0	0
T13	1232696	1232168	0	0
T14	90080	89328	0	0
T15	45216	44576	0	0
T16	225424	224944	0	0
T17	470016	403296	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856100197	5963760	0	0
DstReqKnown_A	3874086	3776219	0	0
SrcAckBusyChk_A	856100197	6696	0	0
SrcBusyKnown_A	856100197	855367223	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	5963760	0	0
T1	14361	291	0	0
T2	768249	32128	0	0
T3	127697	12844	0	0
T4	0	5445	0	0
T6	16987	0	0	0
T7	17702	632	0	0
T8	0	7797	0	0
T13	154087	27009	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	1563	0	0
T52	0	120	0	0
T53	0	49	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3874086	3776219	0	0
T1	118	13	0	0
T2	1651	73	0	0
T3	424	331	0	0
T6	66	3	0	0
T7	72	8	0	0
T13	1231	1151	0	0
T14	89	7	0	0
T15	111	13	0	0
T16	58	2	0	0
T17	120	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	6696	0	0
T1	14361	1	0	0
T2	768249	20	0	0
T3	127697	12	0	0
T4	0	12	0	0
T5	0	5	0	0
T6	16987	0	0	0
T7	17702	1	0	0
T8	0	18	0	0
T9	0	20	0	0
T10	0	1	0	0
T13	154087	64	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	855367223	0	0
T1	14361	13587	0	0
T2	768249	766708	0	0
T3	127697	127619	0	0
T6	16987	16903	0	0
T7	17702	15205	0	0
T13	154087	154021	0	0
T14	11260	11166	0	0
T15	5652	5572	0	0
T16	28178	28118	0	0
T17	58752	50412	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856100197	2909736	0	0
DstReqKnown_A	3874086	3776219	0	0
SrcAckBusyChk_A	856100197	3508	0	0
SrcBusyKnown_A	856100197	855367223	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	2909736	0	0
T1	14361	323	0	0
T2	768249	32159	0	0
T3	127697	13761	0	0
T4	0	4165	0	0
T6	16987	0	0	0
T7	17702	677	0	0
T8	0	7288	0	0
T13	154087	27037	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	1573	0	0
T52	0	55	0	0
T53	0	24	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3874086	3776219	0	0
T1	118	13	0	0
T2	1651	73	0	0
T3	424	331	0	0
T6	66	3	0	0
T7	72	8	0	0
T13	1231	1151	0	0
T14	89	7	0	0
T15	111	13	0	0
T16	58	2	0	0
T17	120	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	3508	0	0
T1	14361	1	0	0
T2	768249	20	0	0
T3	127697	13	0	0
T4	0	9	0	0
T5	0	2	0	0
T6	16987	0	0	0
T7	17702	1	0	0
T8	0	17	0	0
T9	0	20	0	0
T10	0	1	0	0
T13	154087	64	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	855367223	0	0
T1	14361	13587	0	0
T2	768249	766708	0	0
T3	127697	127619	0	0
T6	16987	16903	0	0
T7	17702	15205	0	0
T13	154087	154021	0	0
T14	11260	11166	0	0
T15	5652	5572	0	0
T16	28178	28118	0	0
T17	58752	50412	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856100197	5240955	0	0
DstReqKnown_A	3874086	3776219	0	0
SrcAckBusyChk_A	856100197	5844	0	0
SrcBusyKnown_A	856100197	855367223	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	5240955	0	0
T1	14361	278	0	0
T2	768249	32128	0	0
T3	127697	14932	0	0
T4	0	4216	0	0
T6	16987	0	0	0
T7	17702	614	0	0
T8	0	7720	0	0
T13	154087	27108	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	1555	0	0
T52	0	138	0	0
T53	0	51	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3874086	3776219	0	0
T1	118	13	0	0
T2	1651	73	0	0
T3	424	331	0	0
T6	66	3	0	0
T7	72	8	0	0
T13	1231	1151	0	0
T14	89	7	0	0
T15	111	13	0	0
T16	58	2	0	0
T17	120	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	5844	0	0
T1	14361	1	0	0
T2	768249	20	0	0
T3	127697	14	0	0
T4	0	9	0	0
T5	0	10	0	0
T6	16987	0	0	0
T7	17702	1	0	0
T8	0	18	0	0
T9	0	20	0	0
T10	0	1	0	0
T13	154087	64	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	855367223	0	0
T1	14361	13587	0	0
T2	768249	766708	0	0
T3	127697	127619	0	0
T6	16987	16903	0	0
T7	17702	15205	0	0
T13	154087	154021	0	0
T14	11260	11166	0	0
T15	5652	5572	0	0
T16	28178	28118	0	0
T17	58752	50412	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856100197	2904119	0	0
DstReqKnown_A	3874086	3776219	0	0
SrcAckBusyChk_A	856100197	3472	0	0
SrcBusyKnown_A	856100197	855367223	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	2904119	0	0
T1	14361	312	0	0
T2	768249	32377	0	0
T3	127697	12457	0	0
T4	0	1980	0	0
T6	16987	0	0	0
T7	17702	647	0	0
T8	0	7743	0	0
T13	154087	27123	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	1561	0	0
T52	0	127	0	0
T53	0	64	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3874086	3776219	0	0
T1	118	13	0	0
T2	1651	73	0	0
T3	424	331	0	0
T6	66	3	0	0
T7	72	8	0	0
T13	1231	1151	0	0
T14	89	7	0	0
T15	111	13	0	0
T16	58	2	0	0
T17	120	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	3472	0	0
T1	14361	1	0	0
T2	768249	20	0	0
T3	127697	11	0	0
T4	0	4	0	0
T5	0	3	0	0
T6	16987	0	0	0
T7	17702	1	0	0
T8	0	18	0	0
T9	0	20	0	0
T10	0	1	0	0
T13	154087	64	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	855367223	0	0
T1	14361	13587	0	0
T2	768249	766708	0	0
T3	127697	127619	0	0
T6	16987	16903	0	0
T7	17702	15205	0	0
T13	154087	154021	0	0
T14	11260	11166	0	0
T15	5652	5572	0	0
T16	28178	28118	0	0
T17	58752	50412	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T2,T13,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T2,T13,T3
1	1	Covered	T2,T13,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T2,T13,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T13,T3
1	1	Covered	T2,T13,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T2,T13,T3
0	0	1	Covered	T2,T13,T3
0	0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T2,T13,T3
0	0	1	Covered	T2,T13,T3
0	0	0	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856100197	2906507	0	0
DstReqKnown_A	3874086	3776219	0	0
SrcAckBusyChk_A	856100197	3483	0	0
SrcBusyKnown_A	856100197	855367223	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	2906507	0	0
T2	768249	32129	0	0
T3	127697	13710	0	0
T4	0	6797	0	0
T7	17702	668	0	0
T8	0	7038	0	0
T13	154087	27087	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	1551	0	0
T52	122234	154	0	0
T53	0	67	0	0
T54	0	8	0	0
T55	23839	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3874086	3776219	0	0
T1	118	13	0	0
T2	1651	73	0	0
T3	424	331	0	0
T6	66	3	0	0
T7	72	8	0	0
T13	1231	1151	0	0
T14	89	7	0	0
T15	111	13	0	0
T16	58	2	0	0
T17	120	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	3483	0	0
T2	768249	20	0	0
T3	127697	13	0	0
T4	0	15	0	0
T5	0	6	0	0
T7	17702	1	0	0
T8	0	17	0	0
T9	0	20	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	154087	64	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0
T52	122234	0	0	0
T55	23839	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	855367223	0	0
T1	14361	13587	0	0
T2	768249	766708	0	0
T3	127697	127619	0	0
T6	16987	16903	0	0
T7	17702	15205	0	0
T13	154087	154021	0	0
T14	11260	11166	0	0
T15	5652	5572	0	0
T16	28178	28118	0	0
T17	58752	50412	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Covered	T20,T23,T21
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T21,T22,T24
1	1	Covered	T20,T23,T21

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856100197	6464345	0	0
DstReqKnown_A	3874086	3776219	0	0
SrcAckBusyChk_A	856100197	6327	0	0
SrcBusyKnown_A	856100197	855367223	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	6464345	0	0
T1	14361	329	0	0
T2	768249	32287	0	0
T3	127697	18557	0	0
T4	0	9526	0	0
T6	16987	0	0	0
T7	17702	599	0	0
T8	0	7733	0	0
T13	154087	0	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	1577	0	0
T52	0	75	0	0
T53	0	29	0	0
T54	0	16	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3874086	3776219	0	0
T1	118	13	0	0
T2	1651	73	0	0
T3	424	331	0	0
T6	66	3	0	0
T7	72	8	0	0
T13	1231	1151	0	0
T14	89	7	0	0
T15	111	13	0	0
T16	58	2	0	0
T17	120	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	6327	0	0
T1	14361	1	0	0
T2	768249	20	0	0
T3	127697	14	0	0
T4	0	17	0	0
T5	0	12	0	0
T6	16987	0	0	0
T7	17702	1	0	0
T8	0	18	0	0
T9	0	20	0	0
T10	0	1	0	0
T11	0	7	0	0
T13	154087	0	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	855367223	0	0
T1	14361	13587	0	0
T2	768249	766708	0	0
T3	127697	127619	0	0
T6	16987	16903	0	0
T7	17702	15205	0	0
T13	154087	154021	0	0
T14	11260	11166	0	0
T15	5652	5572	0	0
T16	28178	28118	0	0
T17	58752	50412	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T9,T21,T24
1	1	Covered	T5,T10,T12

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856100197	6041242	0	0
DstReqKnown_A	3874086	3776219	0	0
SrcAckBusyChk_A	856100197	6311	0	0
SrcBusyKnown_A	856100197	855367223	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	6041242	0	0
T1	14361	268	0	0
T2	768249	32090	0	0
T3	127697	13172	0	0
T4	0	4479	0	0
T6	16987	0	0	0
T7	17702	0	0	0
T8	0	7528	0	0
T9	0	2788	0	0
T13	154087	0	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	1573	0	0
T52	0	35	0	0
T53	0	77	0	0
T54	0	42	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3874086	3776219	0	0
T1	118	13	0	0
T2	1651	73	0	0
T3	424	331	0	0
T6	66	3	0	0
T7	72	8	0	0
T13	1231	1151	0	0
T14	89	7	0	0
T15	111	13	0	0
T16	58	2	0	0
T17	120	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	6311	0	0
T1	14361	1	0	0
T2	768249	20	0	0
T3	127697	10	0	0
T4	0	8	0	0
T5	0	2	0	0
T6	16987	0	0	0
T7	17702	0	0	0
T8	0	18	0	0
T9	0	18	0	0
T10	0	1	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	154087	0	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	855367223	0	0
T1	14361	13587	0	0
T2	768249	766708	0	0
T3	127697	127619	0	0
T6	16987	16903	0	0
T7	17702	15205	0	0
T13	154087	154021	0	0
T14	11260	11166	0	0
T15	5652	5572	0	0
T16	28178	28118	0	0
T17	58752	50412	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T2,T3,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T12,T30,T51
1	1	Covered	T12,T20,T23

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	856100197	2737358	0	0
DstReqKnown_A	3874086	3776219	0	0
SrcAckBusyChk_A	856100197	2864	0	0
SrcBusyKnown_A	856100197	855367223	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	2737358	0	0
T1	14361	293	0	0
T2	768249	32240	0	0
T3	127697	15542	0	0
T4	0	8318	0	0
T6	16987	0	0	0
T7	17702	622	0	0
T8	0	7443	0	0
T13	154087	0	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	1567	0	0
T52	0	19	0	0
T53	0	23	0	0
T54	0	24	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3874086	3776219	0	0
T1	118	13	0	0
T2	1651	73	0	0
T3	424	331	0	0
T6	66	3	0	0
T7	72	8	0	0
T13	1231	1151	0	0
T14	89	7	0	0
T15	111	13	0	0
T16	58	2	0	0
T17	120	6	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	2864	0	0
T1	14361	1	0	0
T2	768249	20	0	0
T3	127697	12	0	0
T4	0	15	0	0
T5	0	10	0	0
T6	16987	0	0	0
T7	17702	1	0	0
T8	0	18	0	0
T9	0	20	0	0
T10	0	1	0	0
T11	0	6	0	0
T13	154087	0	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	855367223	0	0
T1	14361	13587	0	0
T2	768249	766708	0	0
T3	127697	127619	0	0
T6	16987	16903	0	0
T7	17702	15205	0	0
T13	154087	154021	0	0
T14	11260	11166	0	0
T15	5652	5572	0	0
T16	28178	28118	0	0
T17	58752	50412	0	0