Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	611401133	5653821	0	0
wdog_bark_thold_rd_A	611401133	145333	0	0
wdog_bite_thold_rd_A	611401133	127526	0	0
wdog_ctrl_rd_A	611401133	128078	0	0
wdog_regwen_rd_A	611401133	145469	0	0
wkup_ctrl_rd_A	611401133	127997	0	0
wkup_thold_rd_A	611401133	146239	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611401133	5653821	0	0
T8	522721	232596	0	0
T9	245954	0	0	0
T10	284943	0	0	0
T11	115791	0	0	0
T12	145105	0	0	0
T13	114084	0	0	0
T14	712809	326974	0	0
T15	862090	209246	0	0
T27	55082	0	0	0
T36	0	129745	0	0
T37	0	56860	0	0
T38	0	176064	0	0
T39	0	127313	0	0
T40	0	259057	0	0
T41	0	247394	0	0
T42	0	113172	0	0
T43	523479	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611401133	145333	0	0
T15	862090	16897	0	0
T36	460121	0	0	0
T43	523479	0	0	0
T44	107654	0	0	0
T47	439411	0	0	0
T48	0	4677	0	0
T52	0	2205	0	0
T71	0	8238	0	0
T72	0	5622	0	0
T90	0	8788	0	0
T91	508636	5247	0	0
T92	0	12693	0	0
T93	0	19130	0	0
T94	0	10294	0	0
T95	55428	0	0	0
T96	34469	0	0	0
T97	40712	0	0	0
T98	53259	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611401133	127526	0	0
T15	862090	14692	0	0
T36	460121	0	0	0
T43	523479	0	0	0
T44	107654	0	0	0
T47	439411	0	0	0
T48	0	4247	0	0
T52	0	2135	0	0
T71	0	6934	0	0
T72	0	4925	0	0
T90	0	7767	0	0
T91	508636	4528	0	0
T92	0	11090	0	0
T93	0	16289	0	0
T94	0	8612	0	0
T95	55428	0	0	0
T96	34469	0	0	0
T97	40712	0	0	0
T98	53259	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611401133	128078	0	0
T15	862090	14836	0	0
T36	460121	0	0	0
T43	523479	0	0	0
T44	107654	0	0	0
T47	439411	0	0	0
T48	0	4376	0	0
T52	0	2084	0	0
T71	0	6916	0	0
T72	0	4785	0	0
T90	0	7552	0	0
T91	508636	4403	0	0
T92	0	11415	0	0
T93	0	17043	0	0
T94	0	8798	0	0
T95	55428	0	0	0
T96	34469	0	0	0
T97	40712	0	0	0
T98	53259	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611401133	145469	0	0
T15	862090	16739	0	0
T36	460121	0	0	0
T43	523479	0	0	0
T44	107654	0	0	0
T47	439411	0	0	0
T48	0	4754	0	0
T52	0	2096	0	0
T71	0	8000	0	0
T72	0	5292	0	0
T90	0	8943	0	0
T91	508636	5030	0	0
T92	0	12878	0	0
T93	0	18547	0	0
T94	0	10528	0	0
T95	55428	0	0	0
T96	34469	0	0	0
T97	40712	0	0	0
T98	53259	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611401133	127997	0	0
T15	862090	15099	0	0
T36	460121	0	0	0
T43	523479	0	0	0
T44	107654	0	0	0
T47	439411	0	0	0
T48	0	4396	0	0
T52	0	1966	0	0
T71	0	7003	0	0
T72	0	4887	0	0
T90	0	7694	0	0
T91	508636	4397	0	0
T92	0	11086	0	0
T93	0	16486	0	0
T94	0	9004	0	0
T95	55428	0	0	0
T96	34469	0	0	0
T97	40712	0	0	0
T98	53259	0	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611401133	146239	0	0
T15	862090	17411	0	0
T36	460121	0	0	0
T43	523479	0	0	0
T44	107654	0	0	0
T47	439411	0	0	0
T48	0	4769	0	0
T52	0	2488	0	0
T71	0	8275	0	0
T72	0	5552	0	0
T90	0	9349	0	0
T91	508636	4986	0	0
T92	0	12528	0	0
T93	0	19304	0	0
T94	0	9994	0	0
T95	55428	0	0	0
T96	34469	0	0	0
T97	40712	0	0	0
T98	53259	0	0	0