Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	295159	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3972798	1		T1	10		T2	10		T3	9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1057707	1		T1	2		T2	2		T3	2
values[0x0]	1515513	1		T1	6		T2	6		T3	5
values[0x1]	1694737	1		T1	8		T2	8		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	133446	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4134511	1		T1	11		T2	10		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16208	1		T8	626		T11	1		T12	2
valid_sources[0x01]	17260	1		T8	708		T13	9		T14	1023
valid_sources[0x02]	16117	1		T8	677		T12	2		T14	994
valid_sources[0x03]	17481	1		T8	708		T12	3		T14	994
valid_sources[0x04]	16476	1		T8	703		T11	2		T14	899
valid_sources[0x05]	17215	1		T8	619		T13	5		T14	970
valid_sources[0x06]	16729	1		T8	599		T12	2		T14	1095
valid_sources[0x07]	15358	1		T5	1		T8	706		T11	1
valid_sources[0x08]	16860	1		T8	776		T14	1073		T15	641
valid_sources[0x09]	16477	1		T8	643		T14	863		T15	666
valid_sources[0x0a]	16062	1		T8	602		T11	3		T14	926
valid_sources[0x0b]	16937	1		T8	668		T14	979		T15	577
valid_sources[0x0c]	17166	1		T5	2		T8	703		T11	1
valid_sources[0x0d]	16491	1		T8	688		T10	1		T14	885
valid_sources[0x0e]	17622	1		T8	666		T11	1		T12	4
valid_sources[0x0f]	16570	1		T8	683		T12	4		T13	1
valid_sources[0x10]	17460	1		T8	691		T11	1		T13	6
valid_sources[0x11]	16064	1		T8	690		T12	1		T14	936
valid_sources[0x12]	16975	1		T8	644		T11	1		T12	2
valid_sources[0x13]	15693	1		T4	2		T8	679		T11	1
valid_sources[0x14]	17844	1		T8	725		T14	1032		T15	584
valid_sources[0x15]	16419	1		T8	683		T14	997		T15	660
valid_sources[0x16]	15655	1		T8	672		T11	1		T12	4
valid_sources[0x17]	16664	1		T8	617		T11	2		T14	1051
valid_sources[0x18]	16406	1		T1	3		T8	662		T11	3
valid_sources[0x19]	17304	1		T8	654		T27	1		T11	1
valid_sources[0x1a]	17202	1		T8	741		T14	981		T15	553
valid_sources[0x1b]	17069	1		T8	711		T27	1		T12	1
valid_sources[0x1c]	16572	1		T5	3		T8	651		T12	2
valid_sources[0x1d]	18443	1		T8	640		T14	971		T15	664
valid_sources[0x1e]	16451	1		T8	719		T13	2		T14	969
valid_sources[0x1f]	17612	1		T8	723		T12	1		T13	10
valid_sources[0x20]	15803	1		T8	710		T11	2		T14	865
valid_sources[0x21]	16297	1		T8	713		T14	928		T15	505
valid_sources[0x22]	16828	1		T8	677		T12	3		T14	988
valid_sources[0x23]	17048	1		T6	17		T8	761		T11	1
valid_sources[0x24]	16712	1		T8	682		T10	13		T11	3
valid_sources[0x25]	17109	1		T8	789		T11	2		T13	5
valid_sources[0x26]	15351	1		T7	3		T8	744		T14	907
valid_sources[0x27]	16112	1		T7	1		T8	691		T11	1
valid_sources[0x28]	15780	1		T8	701		T27	1		T12	2
valid_sources[0x29]	17220	1		T8	720		T12	2		T14	875
valid_sources[0x2a]	15456	1		T8	706		T11	2		T12	1
valid_sources[0x2b]	16105	1		T8	648		T12	4		T14	872
valid_sources[0x2c]	16676	1		T8	618		T11	3		T12	1
valid_sources[0x2d]	16485	1		T8	784		T11	2		T12	2
valid_sources[0x2e]	16172	1		T8	707		T11	2		T12	2
valid_sources[0x2f]	17038	1		T8	588		T14	836		T15	702
valid_sources[0x30]	15868	1		T8	651		T27	1		T11	1
valid_sources[0x31]	15247	1		T8	711		T9	6		T14	1044
valid_sources[0x32]	17467	1		T8	700		T11	2		T12	2
valid_sources[0x33]	15596	1		T8	638		T11	2		T12	3
valid_sources[0x34]	15477	1		T8	751		T11	3		T12	1
valid_sources[0x35]	16830	1		T8	708		T11	1		T14	909
valid_sources[0x36]	16257	1		T8	648		T14	974		T15	685
valid_sources[0x37]	15258	1		T8	690		T11	2		T14	916
valid_sources[0x38]	17068	1		T8	649		T11	1		T14	973
valid_sources[0x39]	15712	1		T8	710		T11	2		T12	1
valid_sources[0x3a]	16670	1		T8	727		T11	4		T14	907
valid_sources[0x3b]	16723	1		T8	656		T14	849		T15	671
valid_sources[0x3c]	17261	1		T8	731		T11	9		T14	838
valid_sources[0x3d]	16940	1		T8	618		T11	1		T12	1
valid_sources[0x3e]	15045	1		T8	651		T12	2		T13	1
valid_sources[0x3f]	17387	1		T8	668		T27	1		T12	1
valid_sources[0x40]	15309	1		T8	653		T11	1		T12	1
valid_sources[0x41]	17109	1		T8	624		T11	2		T12	1
valid_sources[0x42]	17348	1		T8	643		T12	1		T14	1058
valid_sources[0x43]	16325	1		T8	713		T27	1		T12	2
valid_sources[0x44]	17307	1		T8	696		T11	2		T14	925
valid_sources[0x45]	16605	1		T8	682		T11	1		T14	974
valid_sources[0x46]	17457	1		T8	731		T12	1		T13	2
valid_sources[0x47]	18026	1		T8	704		T11	2		T14	946
valid_sources[0x48]	17487	1		T8	671		T14	1062		T15	835
valid_sources[0x49]	17285	1		T8	742		T11	2		T13	3
valid_sources[0x4a]	17358	1		T5	2		T8	734		T11	3
valid_sources[0x4b]	16597	1		T8	716		T27	1		T12	1
valid_sources[0x4c]	16621	1		T8	676		T12	3		T14	912
valid_sources[0x4d]	17962	1		T8	706		T12	1		T13	9
valid_sources[0x4e]	18291	1		T8	680		T11	2		T13	16
valid_sources[0x4f]	16681	1		T8	690		T11	2		T12	1
valid_sources[0x50]	15875	1		T8	664		T12	3		T13	10
valid_sources[0x51]	16092	1		T8	612		T11	1		T12	3
valid_sources[0x52]	16798	1		T8	667		T12	1		T14	992
valid_sources[0x53]	17847	1		T8	597		T12	3		T14	790
valid_sources[0x54]	16103	1		T8	702		T12	1		T14	971
valid_sources[0x55]	16103	1		T3	1		T8	634		T14	1034
valid_sources[0x56]	16250	1		T8	681		T12	1		T14	889
valid_sources[0x57]	14780	1		T8	738		T11	1		T12	2
valid_sources[0x58]	15440	1		T8	640		T12	2		T14	884
valid_sources[0x59]	16976	1		T8	663		T11	2		T12	1
valid_sources[0x5a]	15796	1		T8	689		T11	1		T12	1
valid_sources[0x5b]	15423	1		T8	598		T11	2		T12	1
valid_sources[0x5c]	16453	1		T8	647		T11	3		T12	2
valid_sources[0x5d]	15600	1		T8	712		T12	3		T14	1022
valid_sources[0x5e]	16364	1		T5	1		T7	5		T8	657
valid_sources[0x5f]	15835	1		T5	1		T8	674		T11	2
valid_sources[0x60]	15293	1		T8	683		T11	3		T14	908
valid_sources[0x61]	15796	1		T8	664		T14	946		T15	585
valid_sources[0x62]	16533	1		T8	678		T11	8		T14	921
valid_sources[0x63]	17628	1		T8	664		T14	1104		T15	653
valid_sources[0x64]	17094	1		T8	696		T11	2		T12	3
valid_sources[0x65]	16283	1		T8	698		T11	4		T12	2
valid_sources[0x66]	15967	1		T1	6		T5	1		T8	663
valid_sources[0x67]	16622	1		T8	699		T12	2		T14	957
valid_sources[0x68]	17499	1		T8	717		T11	1		T12	1
valid_sources[0x69]	16228	1		T8	687		T12	1		T14	878
valid_sources[0x6a]	16989	1		T8	598		T14	897		T15	627
valid_sources[0x6b]	16682	1		T8	709		T11	2		T12	2
valid_sources[0x6c]	16772	1		T8	686		T11	1		T12	2
valid_sources[0x6d]	17769	1		T8	750		T14	1120		T15	655
valid_sources[0x6e]	16274	1		T8	638		T11	2		T12	1
valid_sources[0x6f]	16329	1		T8	682		T11	2		T14	1044
valid_sources[0x70]	16169	1		T8	650		T14	895		T15	749
valid_sources[0x71]	15650	1		T8	643		T11	2		T12	1
valid_sources[0x72]	17096	1		T8	684		T12	1		T14	977
valid_sources[0x73]	17151	1		T8	712		T14	1069		T15	559
valid_sources[0x74]	17689	1		T8	671		T12	2		T14	1009
valid_sources[0x75]	17463	1		T8	741		T11	1		T14	934
valid_sources[0x76]	16013	1		T2	16		T8	752		T13	3
valid_sources[0x77]	17655	1		T8	723		T11	1		T12	5
valid_sources[0x78]	17312	1		T8	686		T14	953		T15	763
valid_sources[0x79]	16971	1		T8	648		T27	1		T12	1
valid_sources[0x7a]	15801	1		T8	683		T12	1		T14	940
valid_sources[0x7b]	16239	1		T8	681		T11	1		T12	1
valid_sources[0x7c]	17855	1		T5	1		T8	677		T11	1
valid_sources[0x7d]	17226	1		T8	697		T11	1		T14	1059
valid_sources[0x7e]	15643	1		T8	703		T14	1014		T15	536
valid_sources[0x7f]	17655	1		T8	707		T11	2		T13	2
valid_sources[0x80]	16356	1		T8	750		T27	1		T13	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

992491

1

T2

1

T3

1

T4

1

values[0x0]

all_enables

biggest_size

1491403

1

T1

5

T2

5

T3

4

values[0x1]

all_enables

biggest_size

1488904

1

T1

5

T2

4

T3

4