Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.30			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wdog_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wkup_cause_cdc	98.44	100.00	93.75			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	100.00	90.41			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.52	100.00	98.08			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_ctrl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bark_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bite_thold_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wkup_count_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wdog_count_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T3,T8,T9
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T8,T21,T22
1	1	Covered	T3,T8,T9

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.44	93.75

tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T3,T8,T9
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T24,T26,T41
1	1	Covered	T3,T8,T9

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	36330015	0	0
DstReqKnown_A	28850016	28076336	0	0
SrcAckBusyChk_A	2147483647	40980	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36330015	0	0
T1	258368	8410	0	0
T2	3274664	114112	0	0
T3	454032	40430	0	0
T4	231744	24598	0	0
T5	0	41868	0	0
T6	361392	0	0	0
T7	0	124534	0	0
T8	0	2672	0	0
T9	0	679	0	0
T10	0	1698	0	0
T13	142248	0	0	0
T14	140000	0	0	0
T15	295096	2072	0	0
T16	1966896	225737	0	0
T17	60656	0	0	0
T45	0	844	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28850016	28076336	0	0
T1	528	16	0	0
T2	6536	256	0	0
T3	3624	2336	0	0
T4	1920	1504	0	0
T6	744	16	0	0
T13	1176	640	0	0
T14	672	24	0	0
T15	584	24	0	0
T16	17864	17288	0	0
T17	1000	432	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40980	0	0
T2	3274664	69	0	0
T3	454032	90	0	0
T4	231744	52	0	0
T5	0	97	0	0
T6	361392	0	0	0
T7	0	72	0	0
T8	0	16	0	0
T9	0	7	0	0
T10	0	48	0	0
T11	0	152	0	0
T12	0	6	0	0
T13	142248	0	0	0
T14	140000	0	0	0
T15	295096	0	0	0
T16	1966896	602	0	0
T17	60656	0	0	0
T18	268440	0	0	0
T46	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	258368	257632	0	0
T2	3274664	3267704	0	0
T3	454032	452808	0	0
T4	231744	231160	0	0
T6	361392	360704	0	0
T13	142248	141640	0	0
T14	140000	139200	0	0
T15	295096	227320	0	0
T16	1966896	1966440	0	0
T17	60656	60088	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	703709803	6141494	0	0
DstReqKnown_A	3606252	3509542	0	0
SrcAckBusyChk_A	703709803	7157	0	0
SrcBusyKnown_A	703709803	703023107	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	6141494	0	0
T1	32296	1066	0	0
T2	409333	13229	0	0
T3	56754	5854	0	0
T4	28968	358	0	0
T5	0	2465	0	0
T6	45174	0	0	0
T7	0	15573	0	0
T8	0	334	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	251	0	0
T16	245862	44587	0	0
T17	7582	0	0	0
T45	0	109	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3606252	3509542	0	0
T1	66	2	0	0
T2	817	32	0	0
T3	453	292	0	0
T4	240	188	0	0
T6	93	2	0	0
T13	147	80	0	0
T14	84	3	0	0
T15	73	3	0	0
T16	2233	2161	0	0
T17	125	54	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	7157	0	0
T2	409333	8	0	0
T3	56754	14	0	0
T4	28968	1	0	0
T5	0	7	0	0
T6	45174	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	10	0	0
T11	0	19	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	119	0	0
T17	7582	0	0	0
T18	33555	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	703023107	0	0
T1	32296	32204	0	0
T2	409333	408463	0	0
T3	56754	56601	0	0
T4	28968	28895	0	0
T6	45174	45088	0	0
T13	17781	17705	0	0
T14	17500	17400	0	0
T15	36887	28415	0	0
T16	245862	245805	0	0
T17	7582	7511	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	703709803	3026212	0	0
DstReqKnown_A	3606252	3509542	0	0
SrcAckBusyChk_A	703709803	3634	0	0
SrcBusyKnown_A	703709803	703023107	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	3026212	0	0
T1	32296	1058	0	0
T2	409333	15208	0	0
T3	56754	1689	0	0
T4	28968	3808	0	0
T5	0	3690	0	0
T6	45174	0	0	0
T7	0	15578	0	0
T8	0	299	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	256	0	0
T16	245862	45788	0	0
T17	7582	0	0	0
T45	0	107	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3606252	3509542	0	0
T1	66	2	0	0
T2	817	32	0	0
T3	453	292	0	0
T4	240	188	0	0
T6	93	2	0	0
T13	147	80	0	0
T14	84	3	0	0
T15	73	3	0	0
T16	2233	2161	0	0
T17	125	54	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	3634	0	0
T2	409333	9	0	0
T3	56754	4	0	0
T4	28968	9	0	0
T5	0	10	0	0
T6	45174	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	6	0	0
T11	0	19	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	122	0	0
T17	7582	0	0	0
T18	33555	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	703023107	0	0
T1	32296	32204	0	0
T2	409333	408463	0	0
T3	56754	56601	0	0
T4	28968	28895	0	0
T6	45174	45088	0	0
T13	17781	17705	0	0
T14	17500	17400	0	0
T15	36887	28415	0	0
T16	245862	245805	0	0
T17	7582	7511	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	703709803	5419365	0	0
DstReqKnown_A	3606252	3509542	0	0
SrcAckBusyChk_A	703709803	6253	0	0
SrcBusyKnown_A	703709803	703023107	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	5419365	0	0
T1	32296	1068	0	0
T2	409333	14376	0	0
T3	56754	8114	0	0
T4	28968	1144	0	0
T5	0	4263	0	0
T6	45174	0	0	0
T7	0	15591	0	0
T8	0	342	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	252	0	0
T16	245862	43929	0	0
T17	7582	0	0	0
T45	0	100	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3606252	3509542	0	0
T1	66	2	0	0
T2	817	32	0	0
T3	453	292	0	0
T4	240	188	0	0
T6	93	2	0	0
T13	147	80	0	0
T14	84	3	0	0
T15	73	3	0	0
T16	2233	2161	0	0
T17	125	54	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	6253	0	0
T2	409333	9	0	0
T3	56754	19	0	0
T4	28968	3	0	0
T5	0	11	0	0
T6	45174	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	19	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	117	0	0
T17	7582	0	0	0
T18	33555	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	703023107	0	0
T1	32296	32204	0	0
T2	409333	408463	0	0
T3	56754	56601	0	0
T4	28968	28895	0	0
T6	45174	45088	0	0
T13	17781	17705	0	0
T14	17500	17400	0	0
T15	36887	28415	0	0
T16	245862	245805	0	0
T17	7582	7511	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	703709803	3019344	0	0
DstReqKnown_A	3606252	3509542	0	0
SrcAckBusyChk_A	703709803	3653	0	0
SrcBusyKnown_A	703709803	703023107	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	3019344	0	0
T1	32296	1077	0	0
T2	409333	14431	0	0
T3	56754	5305	0	0
T4	28968	1540	0	0
T5	0	6495	0	0
T6	45174	0	0	0
T7	0	15570	0	0
T8	0	321	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	266	0	0
T16	245862	45444	0	0
T17	7582	0	0	0
T45	0	111	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3606252	3509542	0	0
T1	66	2	0	0
T2	817	32	0	0
T3	453	292	0	0
T4	240	188	0	0
T6	93	2	0	0
T13	147	80	0	0
T14	84	3	0	0
T15	73	3	0	0
T16	2233	2161	0	0
T17	125	54	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	3653	0	0
T2	409333	9	0	0
T3	56754	13	0	0
T4	28968	4	0	0
T5	0	16	0	0
T6	45174	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	19	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	121	0	0
T17	7582	0	0	0
T18	33555	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	703023107	0	0
T1	32296	32204	0	0
T2	409333	408463	0	0
T3	56754	56601	0	0
T4	28968	28895	0	0
T6	45174	45088	0	0
T13	17781	17705	0	0
T14	17500	17400	0	0
T15	36887	28415	0	0
T16	245862	245805	0	0
T17	7582	7511	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	703709803	3047804	0	0
DstReqKnown_A	3606252	3509542	0	0
SrcAckBusyChk_A	703709803	3658	0	0
SrcBusyKnown_A	703709803	703023107	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	3047804	0	0
T1	32296	1064	0	0
T2	409333	15219	0	0
T3	56754	3521	0	0
T4	28968	2974	0	0
T5	0	4432	0	0
T6	45174	0	0	0
T7	0	15559	0	0
T8	0	300	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	262	0	0
T16	245862	45989	0	0
T17	7582	0	0	0
T45	0	115	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3606252	3509542	0	0
T1	66	2	0	0
T2	817	32	0	0
T3	453	292	0	0
T4	240	188	0	0
T6	93	2	0	0
T13	147	80	0	0
T14	84	3	0	0
T15	73	3	0	0
T16	2233	2161	0	0
T17	125	54	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	3658	0	0
T2	409333	9	0	0
T3	56754	9	0	0
T4	28968	7	0	0
T5	0	12	0	0
T6	45174	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	9	0	0
T11	0	19	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	123	0	0
T17	7582	0	0	0
T18	33555	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	703023107	0	0
T1	32296	32204	0	0
T2	409333	408463	0	0
T3	56754	56601	0	0
T4	28968	28895	0	0
T6	45174	45088	0	0
T13	17781	17705	0	0
T14	17500	17400	0	0
T15	36887	28415	0	0
T16	245862	245805	0	0
T17	7582	7511	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T20,T22,T23
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T21,T22,T24
1	1	Covered	T20,T22,T23

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	703709803	6585267	0	0
DstReqKnown_A	3606252	3509542	0	0
SrcAckBusyChk_A	703709803	6788	0	0
SrcBusyKnown_A	703709803	703023107	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	6585267	0	0
T1	32296	1072	0	0
T2	409333	13224	0	0
T3	56754	3543	0	0
T4	28968	4157	0	0
T5	0	8557	0	0
T6	45174	0	0	0
T7	0	15557	0	0
T8	0	297	0	0
T9	0	334	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	267	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T45	0	94	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3606252	3509542	0	0
T1	66	2	0	0
T2	817	32	0	0
T3	453	292	0	0
T4	240	188	0	0
T6	93	2	0	0
T13	147	80	0	0
T14	84	3	0	0
T15	73	3	0	0
T16	2233	2161	0	0
T17	125	54	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	6788	0	0
T2	409333	8	0	0
T3	56754	7	0	0
T4	28968	8	0	0
T5	0	17	0	0
T6	45174	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	7	0	0
T11	0	19	0	0
T12	0	2	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T18	33555	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	703023107	0	0
T1	32296	32204	0	0
T2	409333	408463	0	0
T3	56754	56601	0	0
T4	28968	28895	0	0
T6	45174	45088	0	0
T13	17781	17705	0	0
T14	17500	17400	0	0
T15	36887	28415	0	0
T16	245862	245805	0	0
T17	7582	7511	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T3,T8,T9
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T8,T21,T22
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	703709803	6207168	0	0
DstReqKnown_A	3606252	3509542	0	0
SrcAckBusyChk_A	703709803	6771	0	0
SrcBusyKnown_A	703709803	703023107	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	6207168	0	0
T1	32296	949	0	0
T2	409333	13221	0	0
T3	56754	5597	0	0
T4	28968	4763	0	0
T5	0	3179	0	0
T6	45174	0	0	0
T7	0	15564	0	0
T8	0	439	0	0
T9	0	345	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	258	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T45	0	103	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3606252	3509542	0	0
T1	66	2	0	0
T2	817	32	0	0
T3	453	292	0	0
T4	240	188	0	0
T6	93	2	0	0
T13	147	80	0	0
T14	84	3	0	0
T15	73	3	0	0
T16	2233	2161	0	0
T17	125	54	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	6771	0	0
T2	409333	8	0	0
T3	56754	11	0	0
T4	28968	9	0	0
T5	0	7	0	0
T6	45174	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	19	0	0
T12	0	2	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T18	33555	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	703023107	0	0
T1	32296	32204	0	0
T2	409333	408463	0	0
T3	56754	56601	0	0
T4	28968	28895	0	0
T6	45174	45088	0	0
T13	17781	17705	0	0
T14	17500	17400	0	0
T15	36887	28415	0	0
T16	245862	245805	0	0
T17	7582	7511	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T3,T8,T9
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T24,T26,T41
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	703709803	2883361	0	0
DstReqKnown_A	3606252	3509542	0	0
SrcAckBusyChk_A	703709803	3066	0	0
SrcBusyKnown_A	703709803	703023107	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	2883361	0	0
T1	32296	1056	0	0
T2	409333	15204	0	0
T3	56754	6807	0	0
T4	28968	5854	0	0
T5	0	8787	0	0
T6	45174	0	0	0
T7	0	15542	0	0
T8	0	340	0	0
T10	0	1698	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	260	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T45	0	105	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3606252	3509542	0	0
T1	66	2	0	0
T2	817	32	0	0
T3	453	292	0	0
T4	240	188	0	0
T6	93	2	0	0
T13	147	80	0	0
T14	84	3	0	0
T15	73	3	0	0
T16	2233	2161	0	0
T17	125	54	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	3066	0	0
T2	409333	9	0	0
T3	56754	13	0	0
T4	28968	11	0	0
T5	0	17	0	0
T6	45174	0	0	0
T7	0	9	0	0
T8	0	2	0	0
T10	0	4	0	0
T11	0	19	0	0
T12	0	2	0	0
T13	17781	0	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T18	33555	0	0	0
T46	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	703023107	0	0
T1	32296	32204	0	0
T2	409333	408463	0	0
T3	56754	56601	0	0
T4	28968	28895	0	0
T6	45174	45088	0	0
T13	17781	17705	0	0
T14	17500	17400	0	0
T15	36887	28415	0	0
T16	245862	245805	0	0
T17	7582	7511	0	0