Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	895869413	8519018	0	0
wdog_bark_thold_rd_A	895869413	120989	0	0
wdog_bite_thold_rd_A	895869413	105602	0	0
wdog_ctrl_rd_A	895869413	107289	0	0
wdog_regwen_rd_A	895869413	122808	0	0
wkup_ctrl_rd_A	895869413	107487	0	0
wkup_thold_rd_A	895869413	120682	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895869413	8519018	0	0
T1	811581	5	0	0
T2	114562	0	0	0
T3	782973	7	0	0
T4	96363	7	0	0
T5	27603	0	0	0
T6	93133	0	0	0
T8	14285	311	0	0
T9	54387	5	0	0
T10	0	6	0	0
T12	21689	0	0	0
T13	6206	191	0	0
T51	0	721	0	0
T52	0	418	0	0
T79	0	3	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895869413	120989	0	0
T4	96363	47	0	0
T5	27603	39	0	0
T6	93133	0	0	0
T7	23150	0	0	0
T9	54387	64	0	0
T10	414052	71	0	0
T21	5833	0	0	0
T22	24244	0	0	0
T23	24259	0	0	0
T24	37921	0	0	0
T48	0	4748	0	0
T51	0	74	0	0
T56	0	24	0	0
T76	0	16765	0	0
T80	0	3800	0	0
T81	0	7481	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895869413	105602	0	0
T3	782973	0	0	0
T4	96363	68	0	0
T5	27603	33	0	0
T6	93133	0	0	0
T7	23150	0	0	0
T9	54387	81	0	0
T10	414052	56	0	0
T13	6206	4	0	0
T21	5833	0	0	0
T22	24244	0	0	0
T48	0	4218	0	0
T51	0	36	0	0
T56	0	43	0	0
T80	0	3364	0	0
T81	0	5890	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895869413	107289	0	0
T3	782973	0	0	0
T4	96363	65	0	0
T5	27603	44	0	0
T6	93133	0	0	0
T7	23150	0	0	0
T9	54387	134	0	0
T10	414052	114	0	0
T13	6206	19	0	0
T21	5833	0	0	0
T22	24244	0	0	0
T48	0	4224	0	0
T51	0	64	0	0
T56	0	32	0	0
T80	0	3649	0	0
T81	0	6429	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895869413	122808	0	0
T3	782973	0	0	0
T4	96363	101	0	0
T5	27603	67	0	0
T6	93133	0	0	0
T7	23150	0	0	0
T9	54387	69	0	0
T10	414052	76	0	0
T13	6206	23	0	0
T21	5833	0	0	0
T22	24244	0	0	0
T48	0	5062	0	0
T51	0	80	0	0
T56	0	431	0	0
T80	0	3740	0	0
T81	0	7443	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895869413	107487	0	0
T4	96363	82	0	0
T5	27603	46	0	0
T6	93133	0	0	0
T7	23150	0	0	0
T9	54387	110	0	0
T10	414052	122	0	0
T21	5833	0	0	0
T22	24244	0	0	0
T23	24259	0	0	0
T24	37921	0	0	0
T48	0	4161	0	0
T51	0	78	0	0
T56	0	22	0	0
T76	0	14299	0	0
T80	0	3385	0	0
T81	0	6442	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895869413	120682	0	0
T3	782973	0	0	0
T4	96363	75	0	0
T5	27603	50	0	0
T6	93133	0	0	0
T7	23150	0	0	0
T9	54387	73	0	0
T10	414052	62	0	0
T13	6206	5	0	0
T21	5833	0	0	0
T22	24244	0	0	0
T48	0	4856	0	0
T51	0	43	0	0
T56	0	23	0	0
T80	0	3944	0	0
T81	0	7104	0	0