Unified Coverage Report :: Module :: aon_timer

Module : aon_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	66.67	100.00		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	93.33	100.00	66.67	100.00		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	66.67	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.90	99.82	95.31	100.00		99.35	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
aon_timer_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_aon_intr_flop	100.00	100.00				100.00
u_core	100.00	100.00	100.00			100.00
u_intr_hw	100.00	100.00				100.00	100.00
u_intr_sync	100.00	100.00				100.00
u_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_reg	98.96	99.80	95.71	100.00		99.30	100.00
u_sync_sleep_mode	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : aon_timer

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
ALWAYS	242	3	3	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
81	1	1
82	1	1
83	1	1
84	1	1
107	1	1
163	1	1
167	1	1
199	1	1
201	1	1
202	1	1
203	1	1
204	1	1
207	1	1
208	1	1
209	1	1
210	1	1
228	1	1
229	1	1
232	1	1
239	1	1
242	1	1
243	1	1
245	1	1
249	1	1

---

Cond Coverage for Module : aon_timer

	Total	Covered	Percent
Conditions	12	8	66.67
Logical	12	8	66.67
Non-Logical	0	0
Event	0	0

 LINE       107
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T15,T16
1	1	Not Covered

 LINE       163
 EXPRESSION (aon_wkup_intr_set | aon_wdog_intr_set)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T17,T19,T25
1	0	Covered	T14,T15,T16

 LINE       199
 EXPRESSION (reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe)
             -------------------1------------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Not Covered
1	0	Not Covered

 LINE       239
 EXPRESSION (aon_rst_req_set | aon_rst_req_q)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T17,T19,T20
1	0	Covered	T17,T19,T20

---

Toggle Coverage for Module : aon_timer

	Total	Covered	Percent
Totals	35	35	100.00
Total Bits	356	356	100.00
Total Bits 0->1	178	178	100.00
Total Bits 1->0	178	178	100.00

Ports	35	35	100.00
Port Bits	356	356	100.00
Port Bits 0->1	178	178	100.00
Port Bits 1->0	178	178	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
clk_aon_i	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T8,T2	INPUT
rst_aon_ni	Yes	Yes	T1,T3,T4	Yes	T1,T8,T2	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T12	Yes	T1,T8,T2	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T8,T12	Yes	T1,T8,T12	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T12	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T8,T12	Yes	T1,T8,T12	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
tl_i.a_valid	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
tl_o.a_ready	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	OUTPUT
tl_o.d_error	Yes	Yes	T1,T8,T13	Yes	T1,T8,T13	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T8,*T2	Yes	T1,T8,T2	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T8,*T2	Yes	T1,T8,T2	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T8,T2	Yes	T1,T8,T2	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T14,T16,T17	Yes	T17,T19,T20	INPUT
intr_wkup_timer_expired_o	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
wkup_req_o	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T19,T20,T25	Yes	T17,T19,T20	OUTPUT
sleep_mode_i	Yes	Yes	T15,T16,T17	Yes	T17,T19,T20	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : aon_timer

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	242	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	242	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T14,T15,T16

---

Assert Coverage for Module : aon_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	881999337	881449448	0	0
FpvSecCmRegWeOnehotCheck_A	881999337	90	0	0
IntrWdogKnown_A	881999337	881449448	0	0
IntrWkupKnown_A	881999337	881449448	0	0
RstReqKnown_A	4175807	4116675	0	0
TlOAReadyKnown_A	881999337	881449448	0	0
TlODValidKnown_A	881999337	881449448	0	0
WkupReqKnown_A	4175807	4116675	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881999337	881449448	0	0
T14	19965	19915	0	0
T15	260093	259764	0	0
T16	45875	45797	0	0
T17	107677	107670	0	0
T18	123788	123782	0	0
T19	739289	739213	0	0
T20	483750	483636	0	0
T25	333934	333794	0	0
T26	40918	40828	0	0
T27	126003	125994	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881999337	90	0	0
T28	745016	20	0	0
T29	0	20	0	0
T30	0	10	0	0
T31	0	20	0	0
T32	0	20	0	0
T33	27755	0	0	0
T34	14294	0	0	0
T35	88648	0	0	0
T36	255718	0	0	0
T37	42121	0	0	0
T38	33274	0	0	0
T39	14641	0	0	0
T40	136938	0	0	0
T41	33314	0	0	0

IntrWdogKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881999337	881449448	0	0
T14	19965	19915	0	0
T15	260093	259764	0	0
T16	45875	45797	0	0
T17	107677	107670	0	0
T18	123788	123782	0	0
T19	739289	739213	0	0
T20	483750	483636	0	0
T25	333934	333794	0	0
T26	40918	40828	0	0
T27	126003	125994	0	0

IntrWkupKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881999337	881449448	0	0
T14	19965	19915	0	0
T15	260093	259764	0	0
T16	45875	45797	0	0
T17	107677	107670	0	0
T18	123788	123782	0	0
T19	739289	739213	0	0
T20	483750	483636	0	0
T25	333934	333794	0	0
T26	40918	40828	0	0
T27	126003	125994	0	0

RstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4175807	4116675	0	0
T14	110	18	0	0
T15	21673	21595	0	0
T16	94	17	0	0
T17	55217	54551	0	0
T18	6037	5987	0	0
T19	21742	20891	0	0
T20	38699	37587	0	0
T25	60714	60602	0	0
T26	98	16	0	0
T27	10955	10901	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881999337	881449448	0	0
T14	19965	19915	0	0
T15	260093	259764	0	0
T16	45875	45797	0	0
T17	107677	107670	0	0
T18	123788	123782	0	0
T19	739289	739213	0	0
T20	483750	483636	0	0
T25	333934	333794	0	0
T26	40918	40828	0	0
T27	126003	125994	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881999337	881449448	0	0
T14	19965	19915	0	0
T15	260093	259764	0	0
T16	45875	45797	0	0
T17	107677	107670	0	0
T18	123788	123782	0	0
T19	739289	739213	0	0
T20	483750	483636	0	0
T25	333934	333794	0	0
T26	40918	40828	0	0
T27	126003	125994	0	0

WkupReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4175807	4116675	0	0
T14	110	18	0	0
T15	21673	21595	0	0
T16	94	17	0	0
T17	55217	54551	0	0
T18	6037	5987	0	0
T19	21742	20891	0	0
T20	38699	37587	0	0
T25	60714	60602	0	0
T26	98	16	0	0
T27	10955	10901	0	0