Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	775923878	7460053	0	0
wdog_bark_thold_rd_A	775923878	164019	0	0
wdog_bite_thold_rd_A	775923878	145562	0	0
wdog_ctrl_rd_A	775923878	145578	0	0
wdog_regwen_rd_A	775923878	164850	0	0
wkup_ctrl_rd_A	775923878	144568	0	0
wkup_thold_rd_A	775923878	164218	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	7460053	0	0
T2	410230	2	0	0
T3	177470	0	0	0
T4	48145	0	0	0
T5	0	1	0	0
T7	17797	484	0	0
T8	7223	0	0	0
T9	425348	5	0	0
T10	0	1	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	280	0	0
T16	13670	0	0	0
T54	0	259	0	0
T55	0	2	0	0
T56	0	742	0	0
T94	0	5	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	164019	0	0
T2	410230	17	0	0
T3	177470	0	0	0
T4	48145	0	0	0
T5	50601	0	0	0
T9	425348	0	0	0
T10	410660	0	0	0
T12	0	13	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0
T19	0	5308	0	0
T54	0	12	0	0
T61	0	26826	0	0
T63	0	13644	0	0
T95	0	3988	0	0
T96	0	3594	0	0
T97	0	4899	0	0
T98	0	17344	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	145562	0	0
T2	410230	44	0	0
T3	177470	0	0	0
T4	48145	0	0	0
T5	50601	0	0	0
T6	0	1	0	0
T9	425348	0	0	0
T10	410660	0	0	0
T12	0	57	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0
T19	0	4733	0	0
T54	0	32	0	0
T61	0	23955	0	0
T63	0	12174	0	0
T95	0	3871	0	0
T96	0	2936	0	0
T97	0	4606	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	145578	0	0
T2	410230	35	0	0
T3	177470	0	0	0
T4	48145	0	0	0
T5	50601	0	0	0
T6	0	9	0	0
T9	425348	0	0	0
T10	410660	0	0	0
T12	0	14	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0
T19	0	4881	0	0
T54	0	31	0	0
T61	0	23948	0	0
T63	0	12600	0	0
T95	0	3719	0	0
T96	0	3249	0	0
T97	0	4998	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	164850	0	0
T2	410230	46	0	0
T3	177470	0	0	0
T4	48145	0	0	0
T5	50601	0	0	0
T6	0	12	0	0
T9	425348	0	0	0
T10	410660	0	0	0
T12	0	44	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0
T19	0	5725	0	0
T54	0	30	0	0
T61	0	27273	0	0
T63	0	13679	0	0
T95	0	3514	0	0
T96	0	3721	0	0
T97	0	5163	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	144568	0	0
T2	410230	34	0	0
T3	177470	0	0	0
T4	48145	0	0	0
T5	50601	0	0	0
T9	425348	0	0	0
T10	410660	0	0	0
T12	0	4	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0
T19	0	4902	0	0
T54	0	13	0	0
T61	0	23116	0	0
T63	0	12217	0	0
T95	0	3581	0	0
T96	0	3460	0	0
T97	0	4422	0	0
T98	0	15111	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	164218	0	0
T2	410230	54	0	0
T3	177470	0	0	0
T4	48145	0	0	0
T5	50601	0	0	0
T6	0	7	0	0
T9	425348	0	0	0
T10	410660	0	0	0
T12	0	53	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0
T19	0	5494	0	0
T54	0	28	0	0
T61	0	26219	0	0
T63	0	14014	0	0
T95	0	4030	0	0
T96	0	3820	0	0
T97	0	5019	0	0