Unified Coverage Report :: Module :: aon_timer

Module : aon_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	66.67	100.00		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	93.33	100.00	66.67	100.00		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	66.67	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.90	99.82	95.31	100.00		99.35	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
aon_timer_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_aon_intr_flop	100.00	100.00				100.00
u_core	100.00	100.00	100.00			100.00
u_intr_hw	100.00	100.00				100.00	100.00
u_intr_sync	100.00	100.00				100.00
u_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_reg	98.96	99.80	95.71	100.00		99.30	100.00
u_sync_sleep_mode	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : aon_timer

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
ALWAYS	242	3	3	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
81	1	1
82	1	1
83	1	1
84	1	1
107	1	1
163	1	1
167	1	1
199	1	1
201	1	1
202	1	1
203	1	1
204	1	1
207	1	1
208	1	1
209	1	1
210	1	1
228	1	1
229	1	1
232	1	1
239	1	1
242	1	1
243	1	1
245	1	1
249	1	1

---

Cond Coverage for Module : aon_timer

	Total	Covered	Percent
Conditions	12	8	66.67
Logical	12	8	66.67
Non-Logical	0	0
Event	0	0

 LINE       107
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T19,T20
1	1	Not Covered

 LINE       163
 EXPRESSION (aon_wkup_intr_set | aon_wdog_intr_set)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T19,T29,T30
1	0	Covered	T18,T19,T20

 LINE       199
 EXPRESSION (reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe)
             -------------------1------------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Not Covered
1	0	Not Covered

 LINE       239
 EXPRESSION (aon_rst_req_set | aon_rst_req_q)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T19,T24
1	0	Covered	T18,T19,T24

---

Toggle Coverage for Module : aon_timer

	Total	Covered	Percent
Totals	35	35	100.00
Total Bits	356	356	100.00
Total Bits 0->1	178	178	100.00
Total Bits 1->0	178	178	100.00

Ports	35	35	100.00
Port Bits	356	356	100.00
Port Bits 0->1	178	178	100.00
Port Bits 1->0	178	178	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
clk_aon_i	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
rst_ni	Yes	Yes	T2,T4,T9	Yes	T1,T7,T8	INPUT
rst_aon_ni	Yes	Yes	T2,T4,T9	Yes	T1,T7,T8	INPUT
tl_i.d_ready	Yes	Yes	T7,T2,T16	Yes	T1,T7,T8	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T7,T13	Yes	T1,T7,T13	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	INPUT
tl_i.a_valid	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
tl_o.a_ready	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
tl_o.d_error	Yes	Yes	T7,T2,T15	Yes	T7,T2,T15	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T7,T2	Yes	T1,T7,T2	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T7,T2	Yes	T1,T7,T2	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T7,*T2,*T13	Yes	T1,T7,T8	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T24,T31	INPUT
intr_wkup_timer_expired_o	Yes	Yes	T1,T2,T13	Yes	T1,T2,T13	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T1,T2,T13	Yes	T1,T2,T13	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T1,T2,T13	Yes	T1,T2,T13	OUTPUT
wkup_req_o	Yes	Yes	T3,T11,T18	Yes	T3,T11,T18	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T9,T19,T24	Yes	T3,T9,T11	OUTPUT
sleep_mode_i	Yes	Yes	T18,T20,T21	Yes	T20,T24,T31	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : aon_timer

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	242	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	242	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

---

Assert Coverage for Module : aon_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	763977792	763343184	0	0
FpvSecCmRegWeOnehotCheck_A	763977792	70	0	0
IntrWdogKnown_A	763977792	763343184	0	0
IntrWkupKnown_A	763977792	763343184	0	0
RstReqKnown_A	3640447	3580821	0	0
TlOAReadyKnown_A	763977792	763343184	0	0
TlODValidKnown_A	763977792	763343184	0	0
WkupReqKnown_A	3640447	3580821	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763977792	763343184	0	0
T18	9326	9273	0	0
T19	268033	267767	0	0
T20	135853	135846	0	0
T21	187163	187157	0	0
T22	275692	275684	0	0
T23	372704	372698	0	0
T24	521740	521292	0	0
T29	40314	40227	0	0
T32	543068	543001	0	0
T33	54350	54271	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763977792	70	0	0
T34	740060	20	0	0
T35	0	10	0	0
T36	0	10	0	0
T37	0	10	0	0
T38	0	20	0	0
T39	11122	0	0	0
T40	143958	0	0	0
T41	37060	0	0	0
T42	12416	0	0	0
T43	9402	0	0	0
T44	505207	0	0	0
T45	148738	0	0	0
T46	195628	0	0	0
T47	116558	0	0	0

IntrWdogKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763977792	763343184	0	0
T18	9326	9273	0	0
T19	268033	267767	0	0
T20	135853	135846	0	0
T21	187163	187157	0	0
T22	275692	275684	0	0
T23	372704	372698	0	0
T24	521740	521292	0	0
T29	40314	40227	0	0
T32	543068	543001	0	0
T33	54350	54271	0	0

IntrWkupKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763977792	763343184	0	0
T18	9326	9273	0	0
T19	268033	267767	0	0
T20	135853	135846	0	0
T21	187163	187157	0	0
T22	275692	275684	0	0
T23	372704	372698	0	0
T24	521740	521292	0	0
T29	40314	40227	0	0
T32	543068	543001	0	0
T33	54350	54271	0	0

RstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3640447	3580821	0	0
T18	76	17	0	0
T19	14487	14395	0	0
T20	27444	26783	0	0
T21	7485	7393	0	0
T22	5803	5718	0	0
T23	7605	7507	0	0
T24	6520	5985	0	0
T29	79	21	0	0
T32	3877	3792	0	0
T33	2173	2084	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763977792	763343184	0	0
T18	9326	9273	0	0
T19	268033	267767	0	0
T20	135853	135846	0	0
T21	187163	187157	0	0
T22	275692	275684	0	0
T23	372704	372698	0	0
T24	521740	521292	0	0
T29	40314	40227	0	0
T32	543068	543001	0	0
T33	54350	54271	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763977792	763343184	0	0
T18	9326	9273	0	0
T19	268033	267767	0	0
T20	135853	135846	0	0
T21	187163	187157	0	0
T22	275692	275684	0	0
T23	372704	372698	0	0
T24	521740	521292	0	0
T29	40314	40227	0	0
T32	543068	543001	0	0
T33	54350	54271	0	0

WkupReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3640447	3580821	0	0
T18	76	17	0	0
T19	14487	14395	0	0
T20	27444	26783	0	0
T21	7485	7393	0	0
T22	5803	5718	0	0
T23	7605	7507	0	0
T24	6520	5985	0	0
T29	79	21	0	0
T32	3877	3792	0	0
T33	2173	2084	0	0