Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	683883003	6822914	0	0
wdog_bark_thold_rd_A	683883003	121802	0	0
wdog_bite_thold_rd_A	683883003	106959	0	0
wdog_ctrl_rd_A	683883003	106310	0	0
wdog_regwen_rd_A	683883003	121319	0	0
wkup_ctrl_rd_A	683883003	105083	0	0
wkup_thold_rd_A	683883003	121295	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683883003	6822914	0	0
T14	902212	223078	0	0
T16	483240	147037	0	0
T17	200614	76110	0	0
T32	56166	0	0	0
T33	10851	0	0	0
T37	210188	93604	0	0
T38	396080	120066	0	0
T39	0	231280	0	0
T40	0	25147	0	0
T41	0	83806	0	0
T42	0	308812	0	0
T43	0	211746	0	0
T44	10634	0	0	0
T45	53599	0	0	0
T46	154449	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683883003	121802	0	0
T14	902212	18812	0	0
T16	483240	0	0	0
T17	200614	0	0	0
T32	56166	0	0	0
T33	10851	0	0	0
T37	210188	0	0	0
T38	396080	4789	0	0
T39	0	10298	0	0
T40	0	2420	0	0
T44	10634	0	0	0
T45	53599	0	0	0
T46	154449	0	0	0
T82	0	10889	0	0
T83	0	11960	0	0
T84	0	21910	0	0
T85	0	10758	0	0
T86	0	4352	0	0
T87	0	9895	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683883003	106959	0	0
T14	902212	16162	0	0
T16	483240	0	0	0
T17	200614	0	0	0
T32	56166	0	0	0
T33	10851	0	0	0
T37	210188	0	0	0
T38	396080	4997	0	0
T39	0	9683	0	0
T40	0	1716	0	0
T44	10634	0	0	0
T45	53599	0	0	0
T46	154449	0	0	0
T82	0	9670	0	0
T83	0	9941	0	0
T84	0	18903	0	0
T85	0	9416	0	0
T86	0	4010	0	0
T87	0	9293	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683883003	106310	0	0
T14	902212	16290	0	0
T16	483240	0	0	0
T17	200614	0	0	0
T32	56166	0	0	0
T33	10851	0	0	0
T37	210188	0	0	0
T38	396080	4577	0	0
T39	0	9165	0	0
T40	0	1848	0	0
T44	10634	0	0	0
T45	53599	0	0	0
T46	154449	0	0	0
T82	0	9718	0	0
T83	0	10512	0	0
T84	0	19002	0	0
T85	0	9403	0	0
T86	0	3791	0	0
T87	0	8478	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683883003	121319	0	0
T14	902212	18187	0	0
T16	483240	0	0	0
T17	200614	0	0	0
T32	56166	0	0	0
T33	10851	0	0	0
T37	210188	0	0	0
T38	396080	5353	0	0
T39	0	10001	0	0
T40	0	1909	0	0
T44	10634	0	0	0
T45	53599	0	0	0
T46	154449	0	0	0
T82	0	11141	0	0
T83	0	11830	0	0
T84	0	22006	0	0
T85	0	10883	0	0
T86	0	4461	0	0
T87	0	9887	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683883003	105083	0	0
T14	902212	15688	0	0
T16	483240	0	0	0
T17	200614	0	0	0
T32	56166	0	0	0
T33	10851	0	0	0
T37	210188	0	0	0
T38	396080	4600	0	0
T39	0	8922	0	0
T40	0	1748	0	0
T44	10634	0	0	0
T45	53599	0	0	0
T46	154449	0	0	0
T82	0	9467	0	0
T83	0	10425	0	0
T84	0	18580	0	0
T85	0	9275	0	0
T86	0	3802	0	0
T87	0	8930	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683883003	121295	0	0
T14	902212	18989	0	0
T16	483240	0	0	0
T17	200614	0	0	0
T32	56166	0	0	0
T33	10851	0	0	0
T37	210188	0	0	0
T38	396080	5506	0	0
T39	0	10603	0	0
T40	0	1833	0	0
T44	10634	0	0	0
T45	53599	0	0	0
T46	154449	0	0	0
T82	0	11319	0	0
T83	0	12186	0	0
T84	0	20815	0	0
T85	0	10934	0	0
T86	0	4392	0	0
T87	0	9668	0	0