Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	381814	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4665265	1		T1	16		T2	18		T3	180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1239661	1		T1	1		T2	1		T3	35
values[0x0]	1786151	1		T1	11		T2	12		T3	116
values[0x1]	2021267	1		T1	10		T2	9		T3	118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	170859	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4876220	1		T1	18		T2	18		T3	200

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19327	1		T8	61		T11	1		T19	1307
valid_sources[0x01]	17868	1		T8	333		T19	1301		T20	209
valid_sources[0x02]	19880	1		T8	436		T14	1		T19	1313
valid_sources[0x03]	19360	1		T8	221		T14	2		T19	1273
valid_sources[0x04]	19957	1		T8	263		T11	3		T35	19
valid_sources[0x05]	19170	1		T6	3		T8	72		T11	2
valid_sources[0x06]	19151	1		T8	243		T11	2		T14	6
valid_sources[0x07]	17428	1		T8	425		T9	1		T19	1294
valid_sources[0x08]	19465	1		T8	13		T11	1		T13	1
valid_sources[0x09]	20894	1		T8	284		T11	1		T19	1310
valid_sources[0x0a]	19091	1		T8	208		T11	1		T19	1274
valid_sources[0x0b]	18347	1		T8	135		T11	2		T14	2
valid_sources[0x0c]	19530	1		T8	53		T11	1		T14	1
valid_sources[0x0d]	17965	1		T8	145		T11	1		T14	1
valid_sources[0x0e]	20033	1		T8	178		T14	1		T19	1366
valid_sources[0x0f]	20161	1		T8	355		T11	3		T19	1310
valid_sources[0x10]	21796	1		T8	219		T11	2		T14	1
valid_sources[0x11]	19425	1		T8	316		T11	1		T14	3
valid_sources[0x12]	19817	1		T8	160		T11	1		T18	22
valid_sources[0x13]	18894	1		T8	475		T11	1		T14	3
valid_sources[0x14]	18941	1		T1	2		T8	221		T19	1316
valid_sources[0x15]	19687	1		T8	17		T11	1		T19	1233
valid_sources[0x16]	19986	1		T8	707		T19	1359		T20	168
valid_sources[0x17]	18863	1		T8	340		T14	2		T19	1346
valid_sources[0x18]	19327	1		T8	460		T11	2		T19	1234
valid_sources[0x19]	18303	1		T8	203		T14	3		T19	1242
valid_sources[0x1a]	20150	1		T4	2		T8	165		T11	4
valid_sources[0x1b]	19470	1		T8	353		T14	1		T19	1348
valid_sources[0x1c]	20252	1		T8	752		T11	2		T19	1297
valid_sources[0x1d]	17836	1		T8	375		T11	2		T19	1263
valid_sources[0x1e]	19164	1		T1	1		T8	131		T19	1317
valid_sources[0x1f]	20129	1		T3	10		T8	49		T11	1
valid_sources[0x20]	19811	1		T8	253		T11	6		T14	2
valid_sources[0x21]	20964	1		T8	307		T11	2		T14	1
valid_sources[0x22]	19940	1		T8	16		T11	1		T19	1287
valid_sources[0x23]	18096	1		T1	3		T8	601		T11	1
valid_sources[0x24]	18305	1		T8	196		T19	1208		T20	190
valid_sources[0x25]	19622	1		T1	2		T8	20		T11	5
valid_sources[0x26]	21421	1		T6	1		T8	282		T11	1
valid_sources[0x27]	18816	1		T8	35		T11	1		T19	1308
valid_sources[0x28]	18888	1		T8	218		T11	1		T14	1
valid_sources[0x29]	17829	1		T8	118		T11	3		T14	1
valid_sources[0x2a]	20141	1		T8	397		T11	4		T14	1
valid_sources[0x2b]	18482	1		T8	298		T11	1		T19	1259
valid_sources[0x2c]	21860	1		T7	1		T8	457		T11	1
valid_sources[0x2d]	19837	1		T3	30		T7	2		T8	544
valid_sources[0x2e]	18838	1		T8	267		T11	1		T19	1294
valid_sources[0x2f]	19130	1		T8	389		T11	2		T14	1
valid_sources[0x30]	19239	1		T8	322		T19	1359		T20	197
valid_sources[0x31]	19743	1		T8	187		T19	1296		T20	230
valid_sources[0x32]	19267	1		T8	263		T11	1		T14	2
valid_sources[0x33]	20602	1		T8	935		T14	2		T19	1318
valid_sources[0x34]	20392	1		T3	21		T8	204		T11	1
valid_sources[0x35]	20342	1		T8	178		T11	1		T19	1318
valid_sources[0x36]	19440	1		T3	2		T5	1		T8	234
valid_sources[0x37]	20379	1		T7	1		T8	718		T11	2
valid_sources[0x38]	18766	1		T8	321		T11	1		T19	1295
valid_sources[0x39]	20240	1		T8	916		T11	2		T14	1
valid_sources[0x3a]	19829	1		T8	308		T11	2		T14	1
valid_sources[0x3b]	20237	1		T6	1		T8	217		T11	1
valid_sources[0x3c]	20690	1		T8	430		T11	1		T13	1
valid_sources[0x3d]	18790	1		T8	475		T11	7		T19	1295
valid_sources[0x3e]	19420	1		T5	1		T8	34		T11	3
valid_sources[0x3f]	19483	1		T3	11		T8	133		T19	1307
valid_sources[0x40]	20256	1		T8	246		T11	3		T14	1
valid_sources[0x41]	20512	1		T4	4		T8	56		T11	2
valid_sources[0x42]	19117	1		T3	6		T8	283		T11	3
valid_sources[0x43]	19088	1		T8	366		T11	1		T19	1221
valid_sources[0x44]	19072	1		T8	209		T14	1		T19	1209
valid_sources[0x45]	18078	1		T5	1		T8	173		T11	3
valid_sources[0x46]	20328	1		T8	124		T11	1		T19	1277
valid_sources[0x47]	19381	1		T1	1		T8	531		T11	2
valid_sources[0x48]	17542	1		T8	207		T14	1		T19	1271
valid_sources[0x49]	18492	1		T8	445		T14	2		T19	1280
valid_sources[0x4a]	19816	1		T8	643		T11	1		T19	1279
valid_sources[0x4b]	19584	1		T5	1		T8	405		T11	2
valid_sources[0x4c]	19178	1		T8	17		T11	1		T14	2
valid_sources[0x4d]	20741	1		T6	1		T8	393		T14	2
valid_sources[0x4e]	19392	1		T3	3		T5	1		T8	284
valid_sources[0x4f]	20890	1		T8	391		T11	1		T14	3
valid_sources[0x50]	19752	1		T8	601		T14	1		T19	1226
valid_sources[0x51]	18574	1		T8	192		T11	1		T19	1309
valid_sources[0x52]	18286	1		T8	13		T11	1		T14	4
valid_sources[0x53]	20147	1		T8	678		T11	2		T19	1309
valid_sources[0x54]	20256	1		T8	552		T11	2		T14	2
valid_sources[0x55]	19864	1		T8	143		T11	2		T14	2
valid_sources[0x56]	19231	1		T3	1		T8	424		T19	1322
valid_sources[0x57]	21361	1		T4	3		T8	324		T11	2
valid_sources[0x58]	21107	1		T7	3		T8	219		T11	5
valid_sources[0x59]	18751	1		T8	431		T10	20		T11	5
valid_sources[0x5a]	20020	1		T5	1		T8	359		T11	2
valid_sources[0x5b]	20028	1		T8	283		T11	1		T19	1274
valid_sources[0x5c]	20785	1		T8	407		T11	2		T14	4
valid_sources[0x5d]	20867	1		T1	1		T8	312		T14	1
valid_sources[0x5e]	19774	1		T3	5		T8	316		T11	1
valid_sources[0x5f]	21033	1		T8	447		T11	2		T19	1310
valid_sources[0x60]	19465	1		T8	237		T11	1		T14	2
valid_sources[0x61]	20339	1		T8	111		T19	1316		T20	149
valid_sources[0x62]	19712	1		T1	3		T8	615		T11	3
valid_sources[0x63]	18561	1		T8	243		T14	1		T19	1263
valid_sources[0x64]	20593	1		T8	134		T11	2		T14	1
valid_sources[0x65]	22079	1		T4	7		T5	1		T8	625
valid_sources[0x66]	19828	1		T8	267		T11	1		T19	1312
valid_sources[0x67]	21137	1		T8	192		T11	1		T14	1
valid_sources[0x68]	20067	1		T8	90		T11	2		T14	2
valid_sources[0x69]	19030	1		T8	139		T11	2		T19	1326
valid_sources[0x6a]	19640	1		T8	48		T14	2		T19	1297
valid_sources[0x6b]	18652	1		T8	81		T11	4		T19	1211
valid_sources[0x6c]	18469	1		T3	13		T5	1		T8	380
valid_sources[0x6d]	20257	1		T8	158		T11	3		T14	4
valid_sources[0x6e]	18535	1		T3	13		T7	2		T8	389
valid_sources[0x6f]	20389	1		T8	244		T9	6		T11	1
valid_sources[0x70]	20512	1		T8	523		T14	3		T19	1236
valid_sources[0x71]	19936	1		T8	266		T11	2		T19	1321
valid_sources[0x72]	18387	1		T5	1		T6	1		T8	400
valid_sources[0x73]	20040	1		T3	9		T8	253		T19	1296
valid_sources[0x74]	21207	1		T8	434		T11	1		T14	2
valid_sources[0x75]	18574	1		T8	325		T11	5		T14	1
valid_sources[0x76]	20368	1		T8	409		T11	1		T19	1293
valid_sources[0x77]	18937	1		T5	1		T8	111		T11	2
valid_sources[0x78]	20472	1		T8	160		T14	1		T19	1340
valid_sources[0x79]	20756	1		T8	99		T19	1277		T20	170
valid_sources[0x7a]	18675	1		T8	346		T11	3		T19	1266
valid_sources[0x7b]	19060	1		T8	352		T11	1		T12	308
valid_sources[0x7c]	19765	1		T8	426		T14	1		T19	1318
valid_sources[0x7d]	19262	1		T8	307		T14	1		T19	1334
valid_sources[0x7e]	19245	1		T8	474		T11	1		T14	2
valid_sources[0x7f]	19793	1		T8	362		T11	2		T19	1382
valid_sources[0x80]	19350	1		T8	86		T19	1330		T36	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1162406

1

T1

1

T2

1

T3

17

values[0x0]

all_enables

biggest_size

1753588

1

T1

8

T2

10

T3

83

values[0x1]

all_enables

biggest_size

1749271

1

T1

7

T2

7

T3

80