Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	686000516	5524186	0	0
wdog_bark_thold_rd_A	686000516	134769	0	0
wdog_bite_thold_rd_A	686000516	119675	0	0
wdog_ctrl_rd_A	686000516	119737	0	0
wdog_regwen_rd_A	686000516	137227	0	0
wkup_ctrl_rd_A	686000516	119567	0	0
wkup_thold_hi_rd_A	686000516	136524	0	0
wkup_thold_lo_rd_A	686000516	119533	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686000516	5524186	0	0
T8	374898	82099	0	0
T9	335166	0	0	0
T10	92316	0	0	0
T11	132296	0	0	0
T12	766478	0	0	0
T13	37264	0	0	0
T14	149307	0	0	0
T15	180050	0	0	0
T18	55315	0	0	0
T19	0	375622	0	0
T20	0	59276	0	0
T28	0	89297	0	0
T35	39151	0	0	0
T41	0	189522	0	0
T47	0	95667	0	0
T48	0	58807	0	0
T49	0	205823	0	0
T50	0	82491	0	0
T51	0	84761	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686000516	134769	0	0
T8	374898	7921	0	0
T9	335166	0	0	0
T10	92316	0	0	0
T11	132296	0	0	0
T12	766478	0	0	0
T13	37264	0	0	0
T14	149307	0	0	0
T15	180050	0	0	0
T18	55315	0	0	0
T35	39151	0	0	0
T47	0	9398	0	0
T48	0	5309	0	0
T50	0	8008	0	0
T51	0	8373	0	0
T54	0	1630	0	0
T96	0	10181	0	0
T98	0	8265	0	0
T99	0	8383	0	0
T100	0	8509	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686000516	119675	0	0
T8	374898	6840	0	0
T9	335166	0	0	0
T10	92316	0	0	0
T11	132296	0	0	0
T12	766478	0	0	0
T13	37264	0	0	0
T14	149307	0	0	0
T15	180050	0	0	0
T18	55315	0	0	0
T35	39151	0	0	0
T47	0	8376	0	0
T48	0	4598	0	0
T50	0	7150	0	0
T51	0	7100	0	0
T54	0	1538	0	0
T96	0	9165	0	0
T98	0	7709	0	0
T99	0	7305	0	0
T100	0	7139	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686000516	119737	0	0
T8	374898	6988	0	0
T9	335166	0	0	0
T10	92316	0	0	0
T11	132296	0	0	0
T12	766478	0	0	0
T13	37264	0	0	0
T14	149307	0	0	0
T15	180050	0	0	0
T18	55315	0	0	0
T35	39151	0	0	0
T47	0	8084	0	0
T48	0	4860	0	0
T50	0	7185	0	0
T51	0	7356	0	0
T54	0	1548	0	0
T96	0	8533	0	0
T98	0	7708	0	0
T99	0	7636	0	0
T100	0	7393	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686000516	137227	0	0
T8	374898	8083	0	0
T9	335166	0	0	0
T10	92316	0	0	0
T11	132296	0	0	0
T12	766478	0	0	0
T13	37264	0	0	0
T14	149307	0	0	0
T15	180050	0	0	0
T18	55315	0	0	0
T35	39151	0	0	0
T47	0	9460	0	0
T48	0	5344	0	0
T50	0	7976	0	0
T51	0	8792	0	0
T54	0	1741	0	0
T96	0	10375	0	0
T98	0	8943	0	0
T99	0	8475	0	0
T100	0	8735	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686000516	119567	0	0
T8	374898	6487	0	0
T9	335166	0	0	0
T10	92316	0	0	0
T11	132296	0	0	0
T12	766478	0	0	0
T13	37264	0	0	0
T14	149307	0	0	0
T15	180050	0	0	0
T18	55315	0	0	0
T35	39151	0	0	0
T47	0	8148	0	0
T48	0	4529	0	0
T50	0	7463	0	0
T51	0	7300	0	0
T54	0	1471	0	0
T96	0	9091	0	0
T98	0	7314	0	0
T99	0	7213	0	0
T100	0	7489	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686000516	136524	0	0
T8	374898	7584	0	0
T9	335166	0	0	0
T10	92316	0	0	0
T11	132296	0	0	0
T12	766478	0	0	0
T13	37264	0	0	0
T14	149307	0	0	0
T15	180050	0	0	0
T18	55315	0	0	0
T35	39151	0	0	0
T47	0	9327	0	0
T48	0	5503	0	0
T50	0	8182	0	0
T51	0	8080	0	0
T54	0	1642	0	0
T96	0	10318	0	0
T98	0	8634	0	0
T99	0	8487	0	0
T100	0	9160	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686000516	119533	0	0
T8	374898	6960	0	0
T9	335166	0	0	0
T10	92316	0	0	0
T11	132296	0	0	0
T12	766478	0	0	0
T13	37264	0	0	0
T14	149307	0	0	0
T15	180050	0	0	0
T18	55315	0	0	0
T35	39151	0	0	0
T47	0	8571	0	0
T48	0	4512	0	0
T50	0	7214	0	0
T51	0	7743	0	0
T54	0	1605	0	0
T96	0	9190	0	0
T98	0	7502	0	0
T99	0	7021	0	0
T100	0	7441	0	0