Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
80074 |
0 |
0 |
T1 |
85078 |
26 |
0 |
0 |
T2 |
60766 |
26 |
0 |
0 |
T3 |
5797206 |
269 |
0 |
0 |
T4 |
277438 |
26 |
0 |
0 |
T5 |
288830 |
23 |
0 |
0 |
T6 |
307854 |
23 |
0 |
0 |
T7 |
3541102 |
25 |
0 |
0 |
T8 |
2405578 |
775 |
0 |
0 |
T9 |
2124596 |
25 |
0 |
0 |
T10 |
555806 |
25 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
82129 |
0 |
0 |
T1 |
140570 |
26 |
0 |
0 |
T2 |
100402 |
26 |
0 |
0 |
T3 |
9275546 |
269 |
0 |
0 |
T4 |
461426 |
26 |
0 |
0 |
T5 |
480370 |
23 |
0 |
0 |
T6 |
511970 |
23 |
0 |
0 |
T7 |
5780002 |
25 |
0 |
0 |
T8 |
3842694 |
782 |
0 |
0 |
T9 |
3419820 |
25 |
0 |
0 |
T10 |
924306 |
25 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
7177 |
0 |
0 |
T1 |
115 |
2 |
0 |
0 |
T2 |
82 |
2 |
0 |
0 |
T3 |
36231 |
30 |
0 |
0 |
T4 |
91 |
2 |
0 |
0 |
T5 |
95 |
2 |
0 |
0 |
T6 |
105 |
2 |
0 |
0 |
T7 |
11422 |
3 |
0 |
0 |
T8 |
15619 |
71 |
0 |
0 |
T9 |
11360 |
3 |
0 |
0 |
T10 |
191 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
7409 |
0 |
0 |
T1 |
13988 |
2 |
0 |
0 |
T2 |
9991 |
2 |
0 |
0 |
T3 |
905816 |
30 |
0 |
0 |
T4 |
46088 |
2 |
0 |
0 |
T5 |
47980 |
2 |
0 |
0 |
T6 |
51134 |
2 |
0 |
0 |
T7 |
571147 |
3 |
0 |
0 |
T8 |
374898 |
73 |
0 |
0 |
T9 |
335166 |
3 |
0 |
0 |
T10 |
92316 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
7354 |
0 |
0 |
T1 |
13988 |
2 |
0 |
0 |
T2 |
9991 |
2 |
0 |
0 |
T3 |
905816 |
30 |
0 |
0 |
T4 |
46088 |
2 |
0 |
0 |
T5 |
47980 |
2 |
0 |
0 |
T6 |
51134 |
2 |
0 |
0 |
T7 |
571147 |
3 |
0 |
0 |
T8 |
374898 |
72 |
0 |
0 |
T9 |
335166 |
3 |
0 |
0 |
T10 |
92316 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
7354 |
0 |
0 |
T1 |
115 |
2 |
0 |
0 |
T2 |
82 |
2 |
0 |
0 |
T3 |
36231 |
30 |
0 |
0 |
T4 |
91 |
2 |
0 |
0 |
T5 |
95 |
2 |
0 |
0 |
T6 |
105 |
2 |
0 |
0 |
T7 |
11422 |
3 |
0 |
0 |
T8 |
15619 |
72 |
0 |
0 |
T9 |
11360 |
3 |
0 |
0 |
T10 |
191 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
3684 |
0 |
0 |
T1 |
115 |
1 |
0 |
0 |
T2 |
82 |
1 |
0 |
0 |
T3 |
36231 |
11 |
0 |
0 |
T4 |
91 |
1 |
0 |
0 |
T5 |
95 |
1 |
0 |
0 |
T6 |
105 |
1 |
0 |
0 |
T7 |
11422 |
1 |
0 |
0 |
T8 |
15619 |
35 |
0 |
0 |
T9 |
11360 |
1 |
0 |
0 |
T10 |
191 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
3878 |
0 |
0 |
T1 |
13988 |
1 |
0 |
0 |
T2 |
9991 |
1 |
0 |
0 |
T3 |
905816 |
11 |
0 |
0 |
T4 |
46088 |
1 |
0 |
0 |
T5 |
47980 |
1 |
0 |
0 |
T6 |
51134 |
1 |
0 |
0 |
T7 |
571147 |
1 |
0 |
0 |
T8 |
374898 |
35 |
0 |
0 |
T9 |
335166 |
1 |
0 |
0 |
T10 |
92316 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
3850 |
0 |
0 |
T1 |
13988 |
1 |
0 |
0 |
T2 |
9991 |
1 |
0 |
0 |
T3 |
905816 |
11 |
0 |
0 |
T4 |
46088 |
1 |
0 |
0 |
T5 |
47980 |
1 |
0 |
0 |
T6 |
51134 |
1 |
0 |
0 |
T7 |
571147 |
1 |
0 |
0 |
T8 |
374898 |
35 |
0 |
0 |
T9 |
335166 |
1 |
0 |
0 |
T10 |
92316 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
3850 |
0 |
0 |
T1 |
115 |
1 |
0 |
0 |
T2 |
82 |
1 |
0 |
0 |
T3 |
36231 |
11 |
0 |
0 |
T4 |
91 |
1 |
0 |
0 |
T5 |
95 |
1 |
0 |
0 |
T6 |
105 |
1 |
0 |
0 |
T7 |
11422 |
1 |
0 |
0 |
T8 |
15619 |
35 |
0 |
0 |
T9 |
11360 |
1 |
0 |
0 |
T10 |
191 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
3706 |
0 |
0 |
T1 |
115 |
1 |
0 |
0 |
T2 |
82 |
1 |
0 |
0 |
T3 |
36231 |
11 |
0 |
0 |
T4 |
91 |
1 |
0 |
0 |
T5 |
95 |
1 |
0 |
0 |
T6 |
105 |
1 |
0 |
0 |
T7 |
11422 |
1 |
0 |
0 |
T8 |
15619 |
35 |
0 |
0 |
T9 |
11360 |
1 |
0 |
0 |
T10 |
191 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
3893 |
0 |
0 |
T1 |
13988 |
1 |
0 |
0 |
T2 |
9991 |
1 |
0 |
0 |
T3 |
905816 |
11 |
0 |
0 |
T4 |
46088 |
1 |
0 |
0 |
T5 |
47980 |
1 |
0 |
0 |
T6 |
51134 |
1 |
0 |
0 |
T7 |
571147 |
1 |
0 |
0 |
T8 |
374898 |
35 |
0 |
0 |
T9 |
335166 |
1 |
0 |
0 |
T10 |
92316 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
3864 |
0 |
0 |
T1 |
13988 |
1 |
0 |
0 |
T2 |
9991 |
1 |
0 |
0 |
T3 |
905816 |
11 |
0 |
0 |
T4 |
46088 |
1 |
0 |
0 |
T5 |
47980 |
1 |
0 |
0 |
T6 |
51134 |
1 |
0 |
0 |
T7 |
571147 |
1 |
0 |
0 |
T8 |
374898 |
35 |
0 |
0 |
T9 |
335166 |
1 |
0 |
0 |
T10 |
92316 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
3864 |
0 |
0 |
T1 |
115 |
1 |
0 |
0 |
T2 |
82 |
1 |
0 |
0 |
T3 |
36231 |
11 |
0 |
0 |
T4 |
91 |
1 |
0 |
0 |
T5 |
95 |
1 |
0 |
0 |
T6 |
105 |
1 |
0 |
0 |
T7 |
11422 |
1 |
0 |
0 |
T8 |
15619 |
35 |
0 |
0 |
T9 |
11360 |
1 |
0 |
0 |
T10 |
191 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
6607 |
0 |
0 |
T1 |
115 |
3 |
0 |
0 |
T2 |
82 |
3 |
0 |
0 |
T3 |
36231 |
22 |
0 |
0 |
T4 |
91 |
3 |
0 |
0 |
T5 |
95 |
2 |
0 |
0 |
T6 |
105 |
2 |
0 |
0 |
T7 |
11422 |
2 |
0 |
0 |
T8 |
15619 |
69 |
0 |
0 |
T9 |
11360 |
2 |
0 |
0 |
T10 |
191 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
6810 |
0 |
0 |
T1 |
13988 |
3 |
0 |
0 |
T2 |
9991 |
3 |
0 |
0 |
T3 |
905816 |
22 |
0 |
0 |
T4 |
46088 |
3 |
0 |
0 |
T5 |
47980 |
2 |
0 |
0 |
T6 |
51134 |
2 |
0 |
0 |
T7 |
571147 |
2 |
0 |
0 |
T8 |
374898 |
70 |
0 |
0 |
T9 |
335166 |
2 |
0 |
0 |
T10 |
92316 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
6610 |
0 |
0 |
T1 |
115 |
3 |
0 |
0 |
T2 |
82 |
3 |
0 |
0 |
T3 |
36231 |
22 |
0 |
0 |
T4 |
91 |
3 |
0 |
0 |
T5 |
95 |
2 |
0 |
0 |
T6 |
105 |
2 |
0 |
0 |
T7 |
11422 |
2 |
0 |
0 |
T8 |
15619 |
69 |
0 |
0 |
T9 |
11360 |
2 |
0 |
0 |
T10 |
191 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
6819 |
0 |
0 |
T1 |
13988 |
3 |
0 |
0 |
T2 |
9991 |
3 |
0 |
0 |
T3 |
905816 |
22 |
0 |
0 |
T4 |
46088 |
3 |
0 |
0 |
T5 |
47980 |
2 |
0 |
0 |
T6 |
51134 |
2 |
0 |
0 |
T7 |
571147 |
2 |
0 |
0 |
T8 |
374898 |
70 |
0 |
0 |
T9 |
335166 |
2 |
0 |
0 |
T10 |
92316 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
6217 |
0 |
0 |
T1 |
115 |
2 |
0 |
0 |
T2 |
82 |
2 |
0 |
0 |
T3 |
36231 |
22 |
0 |
0 |
T4 |
91 |
2 |
0 |
0 |
T5 |
95 |
2 |
0 |
0 |
T6 |
105 |
2 |
0 |
0 |
T7 |
11422 |
2 |
0 |
0 |
T8 |
15619 |
59 |
0 |
0 |
T9 |
11360 |
2 |
0 |
0 |
T10 |
191 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
6441 |
0 |
0 |
T1 |
13988 |
2 |
0 |
0 |
T2 |
9991 |
2 |
0 |
0 |
T3 |
905816 |
22 |
0 |
0 |
T4 |
46088 |
2 |
0 |
0 |
T5 |
47980 |
2 |
0 |
0 |
T6 |
51134 |
2 |
0 |
0 |
T7 |
571147 |
2 |
0 |
0 |
T8 |
374898 |
61 |
0 |
0 |
T9 |
335166 |
2 |
0 |
0 |
T10 |
92316 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
6391 |
0 |
0 |
T1 |
13988 |
2 |
0 |
0 |
T2 |
9991 |
2 |
0 |
0 |
T3 |
905816 |
22 |
0 |
0 |
T4 |
46088 |
2 |
0 |
0 |
T5 |
47980 |
2 |
0 |
0 |
T6 |
51134 |
2 |
0 |
0 |
T7 |
571147 |
2 |
0 |
0 |
T8 |
374898 |
60 |
0 |
0 |
T9 |
335166 |
2 |
0 |
0 |
T10 |
92316 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
6391 |
0 |
0 |
T1 |
115 |
2 |
0 |
0 |
T2 |
82 |
2 |
0 |
0 |
T3 |
36231 |
22 |
0 |
0 |
T4 |
91 |
2 |
0 |
0 |
T5 |
95 |
2 |
0 |
0 |
T6 |
105 |
2 |
0 |
0 |
T7 |
11422 |
2 |
0 |
0 |
T8 |
15619 |
60 |
0 |
0 |
T9 |
11360 |
2 |
0 |
0 |
T10 |
191 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
3683 |
0 |
0 |
T1 |
115 |
1 |
0 |
0 |
T2 |
82 |
1 |
0 |
0 |
T3 |
36231 |
11 |
0 |
0 |
T4 |
91 |
1 |
0 |
0 |
T5 |
95 |
1 |
0 |
0 |
T6 |
105 |
1 |
0 |
0 |
T7 |
11422 |
1 |
0 |
0 |
T8 |
15619 |
35 |
0 |
0 |
T9 |
11360 |
1 |
0 |
0 |
T10 |
191 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
3885 |
0 |
0 |
T1 |
13988 |
1 |
0 |
0 |
T2 |
9991 |
1 |
0 |
0 |
T3 |
905816 |
11 |
0 |
0 |
T4 |
46088 |
1 |
0 |
0 |
T5 |
47980 |
1 |
0 |
0 |
T6 |
51134 |
1 |
0 |
0 |
T7 |
571147 |
1 |
0 |
0 |
T8 |
374898 |
35 |
0 |
0 |
T9 |
335166 |
1 |
0 |
0 |
T10 |
92316 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
3854 |
0 |
0 |
T1 |
13988 |
1 |
0 |
0 |
T2 |
9991 |
1 |
0 |
0 |
T3 |
905816 |
11 |
0 |
0 |
T4 |
46088 |
1 |
0 |
0 |
T5 |
47980 |
1 |
0 |
0 |
T6 |
51134 |
1 |
0 |
0 |
T7 |
571147 |
1 |
0 |
0 |
T8 |
374898 |
35 |
0 |
0 |
T9 |
335166 |
1 |
0 |
0 |
T10 |
92316 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
3854 |
0 |
0 |
T1 |
115 |
1 |
0 |
0 |
T2 |
82 |
1 |
0 |
0 |
T3 |
36231 |
11 |
0 |
0 |
T4 |
91 |
1 |
0 |
0 |
T5 |
95 |
1 |
0 |
0 |
T6 |
105 |
1 |
0 |
0 |
T7 |
11422 |
1 |
0 |
0 |
T8 |
15619 |
35 |
0 |
0 |
T9 |
11360 |
1 |
0 |
0 |
T10 |
191 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
3688 |
0 |
0 |
T1 |
115 |
1 |
0 |
0 |
T2 |
82 |
1 |
0 |
0 |
T3 |
36231 |
11 |
0 |
0 |
T4 |
91 |
1 |
0 |
0 |
T5 |
95 |
1 |
0 |
0 |
T6 |
105 |
1 |
0 |
0 |
T7 |
11422 |
1 |
0 |
0 |
T8 |
15619 |
35 |
0 |
0 |
T9 |
11360 |
1 |
0 |
0 |
T10 |
191 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
3880 |
0 |
0 |
T1 |
13988 |
1 |
0 |
0 |
T2 |
9991 |
1 |
0 |
0 |
T3 |
905816 |
11 |
0 |
0 |
T4 |
46088 |
1 |
0 |
0 |
T5 |
47980 |
1 |
0 |
0 |
T6 |
51134 |
1 |
0 |
0 |
T7 |
571147 |
1 |
0 |
0 |
T8 |
374898 |
35 |
0 |
0 |
T9 |
335166 |
1 |
0 |
0 |
T10 |
92316 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
3851 |
0 |
0 |
T1 |
13988 |
1 |
0 |
0 |
T2 |
9991 |
1 |
0 |
0 |
T3 |
905816 |
11 |
0 |
0 |
T4 |
46088 |
1 |
0 |
0 |
T5 |
47980 |
1 |
0 |
0 |
T6 |
51134 |
1 |
0 |
0 |
T7 |
571147 |
1 |
0 |
0 |
T8 |
374898 |
35 |
0 |
0 |
T9 |
335166 |
1 |
0 |
0 |
T10 |
92316 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
3851 |
0 |
0 |
T1 |
115 |
1 |
0 |
0 |
T2 |
82 |
1 |
0 |
0 |
T3 |
36231 |
11 |
0 |
0 |
T4 |
91 |
1 |
0 |
0 |
T5 |
95 |
1 |
0 |
0 |
T6 |
105 |
1 |
0 |
0 |
T7 |
11422 |
1 |
0 |
0 |
T8 |
15619 |
35 |
0 |
0 |
T9 |
11360 |
1 |
0 |
0 |
T10 |
191 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
6619 |
0 |
0 |
T1 |
115 |
3 |
0 |
0 |
T2 |
82 |
3 |
0 |
0 |
T3 |
36231 |
22 |
0 |
0 |
T4 |
91 |
3 |
0 |
0 |
T5 |
95 |
2 |
0 |
0 |
T6 |
105 |
2 |
0 |
0 |
T7 |
11422 |
2 |
0 |
0 |
T8 |
15619 |
69 |
0 |
0 |
T9 |
11360 |
2 |
0 |
0 |
T10 |
191 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
6831 |
0 |
0 |
T1 |
13988 |
3 |
0 |
0 |
T2 |
9991 |
3 |
0 |
0 |
T3 |
905816 |
22 |
0 |
0 |
T4 |
46088 |
3 |
0 |
0 |
T5 |
47980 |
2 |
0 |
0 |
T6 |
51134 |
2 |
0 |
0 |
T7 |
571147 |
2 |
0 |
0 |
T8 |
374898 |
70 |
0 |
0 |
T9 |
335166 |
2 |
0 |
0 |
T10 |
92316 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3157682 |
2919 |
0 |
0 |
T1 |
115 |
1 |
0 |
0 |
T2 |
82 |
1 |
0 |
0 |
T3 |
36231 |
11 |
0 |
0 |
T4 |
91 |
1 |
0 |
0 |
T5 |
95 |
1 |
0 |
0 |
T6 |
105 |
1 |
0 |
0 |
T7 |
11422 |
1 |
0 |
0 |
T8 |
15619 |
26 |
0 |
0 |
T9 |
11360 |
1 |
0 |
0 |
T10 |
191 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
686000516 |
3119 |
0 |
0 |
T1 |
13988 |
1 |
0 |
0 |
T2 |
9991 |
1 |
0 |
0 |
T3 |
905816 |
11 |
0 |
0 |
T4 |
46088 |
1 |
0 |
0 |
T5 |
47980 |
1 |
0 |
0 |
T6 |
51134 |
1 |
0 |
0 |
T7 |
571147 |
1 |
0 |
0 |
T8 |
374898 |
26 |
0 |
0 |
T9 |
335166 |
1 |
0 |
0 |
T10 |
92316 |
1 |
0 |
0 |