Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	764035988	5064910	0	0
wdog_bark_thold_rd_A	764035988	160124	0	0
wdog_bite_thold_rd_A	764035988	141309	0	0
wdog_ctrl_rd_A	764035988	139069	0	0
wdog_regwen_rd_A	764035988	158266	0	0
wkup_ctrl_rd_A	764035988	139183	0	0
wkup_thold_hi_rd_A	764035988	160916	0	0
wkup_thold_lo_rd_A	764035988	139492	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764035988	5064910	0	0
T9	215614	45993	0	0
T10	35992	0	0	0
T11	103845	0	0	0
T12	13018	0	0	0
T13	773088	274536	0	0
T14	37347	0	0	0
T15	998264	0	0	0
T16	15047	0	0	0
T17	224492	75705	0	0
T37	0	127831	0	0
T38	0	29762	0	0
T39	0	227784	0	0
T40	0	57821	0	0
T41	0	45211	0	0
T42	0	109392	0	0
T43	0	144967	0	0
T44	331993	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764035988	160124	0	0
T9	215614	4822	0	0
T10	35992	0	0	0
T11	103845	0	0	0
T12	13018	0	0	0
T13	773088	0	0	0
T14	37347	0	0	0
T15	998264	0	0	0
T16	15047	0	0	0
T17	224492	0	0	0
T39	0	23686	0	0
T42	0	11120	0	0
T44	331993	0	0	0
T91	0	10872	0	0
T94	0	20364	0	0
T95	0	2090	0	0
T96	0	16937	0	0
T97	0	2247	0	0
T98	0	21588	0	0
T99	0	25730	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764035988	141309	0	0
T9	215614	4366	0	0
T10	35992	0	0	0
T11	103845	0	0	0
T12	13018	0	0	0
T13	773088	0	0	0
T14	37347	0	0	0
T15	998264	0	0	0
T16	15047	0	0	0
T17	224492	0	0	0
T39	0	20202	0	0
T42	0	10381	0	0
T44	331993	0	0	0
T91	0	9640	0	0
T94	0	17965	0	0
T95	0	1969	0	0
T96	0	14224	0	0
T97	0	2013	0	0
T98	0	18574	0	0
T99	0	23785	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764035988	139069	0	0
T9	215614	3985	0	0
T10	35992	0	0	0
T11	103845	0	0	0
T12	13018	0	0	0
T13	773088	0	0	0
T14	37347	0	0	0
T15	998264	0	0	0
T16	15047	0	0	0
T17	224492	0	0	0
T39	0	20483	0	0
T42	0	10118	0	0
T44	331993	0	0	0
T91	0	9232	0	0
T94	0	18060	0	0
T95	0	1701	0	0
T96	0	14610	0	0
T97	0	2239	0	0
T98	0	17562	0	0
T99	0	23030	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764035988	158266	0	0
T9	215614	4677	0	0
T10	35992	0	0	0
T11	103845	0	0	0
T12	13018	0	0	0
T13	773088	0	0	0
T14	37347	0	0	0
T15	998264	0	0	0
T16	15047	0	0	0
T17	224492	0	0	0
T39	0	22457	0	0
T42	0	11316	0	0
T44	331993	0	0	0
T91	0	10902	0	0
T94	0	20014	0	0
T95	0	2298	0	0
T96	0	17433	0	0
T97	0	2525	0	0
T98	0	20516	0	0
T99	0	26020	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764035988	139183	0	0
T9	215614	3996	0	0
T10	35992	0	0	0
T11	103845	0	0	0
T12	13018	0	0	0
T13	773088	0	0	0
T14	37347	0	0	0
T15	998264	0	0	0
T16	15047	0	0	0
T17	224492	0	0	0
T39	0	20569	0	0
T42	0	10199	0	0
T44	331993	0	0	0
T91	0	9145	0	0
T94	0	17435	0	0
T95	0	1970	0	0
T96	0	14931	0	0
T97	0	2082	0	0
T98	0	18321	0	0
T99	0	22564	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764035988	160916	0	0
T9	215614	4767	0	0
T10	35992	0	0	0
T11	103845	0	0	0
T12	13018	0	0	0
T13	773088	0	0	0
T14	37347	0	0	0
T15	998264	0	0	0
T16	15047	0	0	0
T17	224492	0	0	0
T39	0	23380	0	0
T42	0	11576	0	0
T44	331993	0	0	0
T91	0	10847	0	0
T94	0	20252	0	0
T95	0	2168	0	0
T96	0	16669	0	0
T97	0	2520	0	0
T98	0	21447	0	0
T99	0	26319	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764035988	139492	0	0
T9	215614	3979	0	0
T10	35992	0	0	0
T11	103845	0	0	0
T12	13018	0	0	0
T13	773088	0	0	0
T14	37347	0	0	0
T15	998264	0	0	0
T16	15047	0	0	0
T17	224492	0	0	0
T39	0	20572	0	0
T42	0	10042	0	0
T44	331993	0	0	0
T91	0	9364	0	0
T94	0	17773	0	0
T95	0	1849	0	0
T96	0	14787	0	0
T97	0	2149	0	0
T98	0	18566	0	0
T99	0	22354	0	0