Module Definition
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Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.10 94.74 71.83 89.83 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 74.06 92.86 67.35 86.05 50.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.11 100.00 90.14 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.11 100.00 90.14 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.44 100.00 93.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 100.00 90.41 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
97.73 90.91
tb.dut.u_reg.u_wkup_ctrl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wkup_thold_hi_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wkup_thold_lo_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wdog_bark_thold_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wdog_bite_thold_cdc

SCORECOND
92.86 71.43
tb.dut.u_reg.u_wkup_count_hi_cdc

SCORECOND
98.21 92.86
tb.dut.u_reg.u_wkup_count_lo_cdc

SCORECOND
98.21 92.86
tb.dut.u_reg.u_wdog_count_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wdog_ctrl_cdc

TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T5
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T3,T5

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
98.44 93.75
tb.dut.u_reg.u_wkup_cause_cdc

TotalCoveredPercent
Conditions161593.75
Logical161593.75
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT32,T33,T34

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T9
11CoveredT2,T3,T4

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 2147483647 42891107 0 0
DstReqKnown_A 33737030 32834560 0 0
SrcAckBusyChk_A 2147483647 44844 0 0
SrcBusyKnown_A 2147483647 2147483647 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 42891107 0 0
T1 199390 13592 0 0
T2 196560 11758 0 0
T3 8909050 222553 0 0
T4 286800 20079 0 0
T5 77380 3858 0 0
T6 2075620 59041 0 0
T7 130090 6703 0 0
T8 338290 24723 0 0
T9 2156140 130365 0 0
T10 359920 33509 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 33737030 32834560 0 0
T1 880 160 0 0
T2 970 220 0 0
T3 323950 314270 0 0
T4 1130 180 0 0
T5 950 250 0 0
T6 166040 159380 0 0
T7 880 180 0 0
T8 670 170 0 0
T9 179660 178440 0 0
T10 710 150 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 44844 0 0
T1 199390 15 0 0
T2 196560 15 0 0
T3 8909050 233 0 0
T4 286800 16 0 0
T5 77380 15 0 0
T6 2075620 135 0 0
T7 130090 15 0 0
T8 338290 15 0 0
T9 2156140 319 0 0
T10 359920 14 0 0
T11 0 12 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 199390 198840 0 0
T2 196560 195680 0 0
T3 8909050 8907970 0 0
T4 286800 286200 0 0
T5 77380 76440 0 0
T6 2075620 2075010 0 0
T7 130090 129450 0 0
T8 338290 337550 0 0
T9 2156140 2152450 0 0
T10 359920 359200 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 5623552 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 5857 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 5623552 0 0
T1 19939 1560 0 0
T2 19656 1505 0 0
T3 890905 32710 0 0
T4 28680 3179 0 0
T5 7738 497 0 0
T6 207562 8693 0 0
T7 13009 961 0 0
T8 33829 2917 0 0
T9 215614 18934 0 0
T10 35992 3986 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 5857 0 0
T1 19939 2 0 0
T2 19656 2 0 0
T3 890905 34 0 0
T4 28680 3 0 0
T5 7738 2 0 0
T6 207562 20 0 0
T7 13009 2 0 0
T8 33829 2 0 0
T9 215614 46 0 0
T10 35992 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 5905607 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 6253 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 5905607 0 0
T1 19939 1556 0 0
T2 19656 1486 0 0
T3 890905 30264 0 0
T4 28680 1975 0 0
T5 7738 480 0 0
T6 207562 8212 0 0
T7 13009 944 0 0
T8 33829 2894 0 0
T9 215614 18031 0 0
T10 35992 3982 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 6253 0 0
T1 19939 2 0 0
T2 19656 2 0 0
T3 890905 33 0 0
T4 28680 2 0 0
T5 7738 2 0 0
T6 207562 19 0 0
T7 13009 2 0 0
T8 33829 2 0 0
T9 215614 44 0 0
T10 35992 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 2944012 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 3274 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 2944012 0 0
T1 19939 891 0 0
T2 19656 736 0 0
T3 890905 12398 0 0
T4 28680 952 0 0
T5 7738 284 0 0
T6 207562 3220 0 0
T7 13009 387 0 0
T8 33829 1440 0 0
T9 215614 8143 0 0
T10 35992 1991 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 3274 0 0
T1 19939 1 0 0
T2 19656 1 0 0
T3 890905 14 0 0
T4 28680 1 0 0
T5 7738 1 0 0
T6 207562 8 0 0
T7 13009 1 0 0
T8 33829 1 0 0
T9 215614 21 0 0
T10 35992 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 2928298 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 3247 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 2928298 0 0
T1 19939 893 0 0
T2 19656 750 0 0
T3 890905 12533 0 0
T4 28680 958 0 0
T5 7738 296 0 0
T6 207562 3283 0 0
T7 13009 395 0 0
T8 33829 1448 0 0
T9 215614 8118 0 0
T10 35992 1993 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 3247 0 0
T1 19939 1 0 0
T2 19656 1 0 0
T3 890905 14 0 0
T4 28680 1 0 0
T5 7738 1 0 0
T6 207562 8 0 0
T7 13009 1 0 0
T8 33829 1 0 0
T9 215614 21 0 0
T10 35992 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 5142010 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 5425 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 5142010 0 0
T1 19939 1552 0 0
T2 19656 1458 0 0
T3 890905 26147 0 0
T4 28680 1983 0 0
T5 7738 459 0 0
T6 207562 6813 0 0
T7 13009 923 0 0
T8 33829 2872 0 0
T9 215614 14935 0 0
T10 35992 3978 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 5425 0 0
T1 19939 2 0 0
T2 19656 2 0 0
T3 890905 28 0 0
T4 28680 2 0 0
T5 7738 2 0 0
T6 207562 16 0 0
T7 13009 2 0 0
T8 33829 2 0 0
T9 215614 36 0 0
T10 35992 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 2927263 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 3257 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 2927263 0 0
T1 19939 889 0 0
T2 19656 728 0 0
T3 890905 12256 0 0
T4 28680 940 0 0
T5 7738 281 0 0
T6 207562 3272 0 0
T7 13009 385 0 0
T8 33829 1432 0 0
T9 215614 8148 0 0
T10 35992 1989 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 3257 0 0
T1 19939 1 0 0
T2 19656 1 0 0
T3 890905 14 0 0
T4 28680 1 0 0
T5 7738 1 0 0
T6 207562 8 0 0
T7 13009 1 0 0
T8 33829 1 0 0
T9 215614 21 0 0
T10 35992 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 2972928 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 3301 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 2972928 0 0
T1 19939 887 0 0
T2 19656 718 0 0
T3 890905 12112 0 0
T4 28680 933 0 0
T5 7738 269 0 0
T6 207562 3201 0 0
T7 13009 381 0 0
T8 33829 1426 0 0
T9 215614 8051 0 0
T10 35992 1987 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 3301 0 0
T1 19939 1 0 0
T2 19656 1 0 0
T3 890905 14 0 0
T4 28680 1 0 0
T5 7738 1 0 0
T6 207562 8 0 0
T7 13009 1 0 0
T8 33829 1 0 0
T9 215614 21 0 0
T10 35992 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T5
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T3,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 6112794 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 5799 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 6112794 0 0
T1 19939 2014 0 0
T2 19656 1728 0 0
T3 890905 36901 0 0
T4 28680 4119 0 0
T5 7738 510 0 0
T6 207562 10356 0 0
T7 13009 969 0 0
T8 33829 4434 0 0
T9 215614 19783 0 0
T10 35992 4989 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 5799 0 0
T1 19939 2 0 0
T2 19656 2 0 0
T3 890905 34 0 0
T4 28680 2 0 0
T5 7738 2 0 0
T6 207562 20 0 0
T7 13009 2 0 0
T8 33829 2 0 0
T9 215614 46 0 0
T10 35992 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T5
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T3,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 5746528 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 5821 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 5746528 0 0
T1 19939 2006 0 0
T2 19656 1683 0 0
T3 890905 32614 0 0
T4 28680 4061 0 0
T5 7738 488 0 0
T6 207562 8512 0 0
T7 13009 937 0 0
T8 33829 4391 0 0
T9 215614 18852 0 0
T10 35992 4981 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 5821 0 0
T1 19939 2 0 0
T2 19656 2 0 0
T3 890905 34 0 0
T4 28680 2 0 0
T5 7738 2 0 0
T6 207562 20 0 0
T7 13009 2 0 0
T8 33829 2 0 0
T9 215614 46 0 0
T10 35992 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
TotalCoveredPercent
Conditions161593.75
Logical161593.75
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT32,T33,T34

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T9
11CoveredT2,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 764035988 2588115 0 0
DstReqKnown_A 3373703 3283456 0 0
SrcAckBusyChk_A 764035988 2610 0 0
SrcBusyKnown_A 764035988 763299200 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 2588115 0 0
T1 19939 1344 0 0
T2 19656 966 0 0
T3 890905 14618 0 0
T4 28680 979 0 0
T5 7738 294 0 0
T6 207562 3479 0 0
T7 13009 421 0 0
T8 33829 1469 0 0
T9 215614 7370 0 0
T10 35992 3633 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3373703 3283456 0 0
T1 88 16 0 0
T2 97 22 0 0
T3 32395 31427 0 0
T4 113 18 0 0
T5 95 25 0 0
T6 16604 15938 0 0
T7 88 18 0 0
T8 67 17 0 0
T9 17966 17844 0 0
T10 71 15 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 2610 0 0
T1 19939 1 0 0
T2 19656 1 0 0
T3 890905 14 0 0
T4 28680 1 0 0
T5 7738 1 0 0
T6 207562 8 0 0
T7 13009 1 0 0
T8 33829 1 0 0
T9 215614 17 0 0
T10 35992 0 0 0
T11 0 12 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 764035988 763299200 0 0
T1 19939 19884 0 0
T2 19656 19568 0 0
T3 890905 890797 0 0
T4 28680 28620 0 0
T5 7738 7644 0 0
T6 207562 207501 0 0
T7 13009 12945 0 0
T8 33829 33755 0 0
T9 215614 215245 0 0
T10 35992 35920 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%