Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	702764201	4843726	0	0
wdog_bark_thold_rd_A	702764201	124884	0	0
wdog_bite_thold_rd_A	702764201	111566	0	0
wdog_ctrl_rd_A	702764201	110140	0	0
wdog_regwen_rd_A	702764201	127365	0	0
wkup_ctrl_rd_A	702764201	110823	0	0
wkup_thold_hi_rd_A	702764201	125726	0	0
wkup_thold_lo_rd_A	702764201	110418	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702764201	4843726	0	0
T8	265096	98483	0	0
T9	160431	0	0	0
T10	11146	0	0	0
T11	236884	0	0	0
T12	654875	0	0	0
T13	203957	47057	0	0
T14	0	47163	0	0
T26	0	194751	0	0
T32	19513	0	0	0
T33	177243	0	0	0
T34	198937	0	0	0
T38	0	257173	0	0
T45	0	215098	0	0
T46	0	14265	0	0
T47	0	177902	0	0
T48	0	161233	0	0
T49	0	43839	0	0
T50	999460	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702764201	124884	0	0
T13	203957	2703	0	0
T14	129112	0	0	0
T29	157686	0	0	0
T30	172312	0	0	0
T31	12607	0	0	0
T38	713673	0	0	0
T45	0	20650	0	0
T46	0	697	0	0
T50	999460	0	0	0
T51	920271	0	0	0
T52	727200	0	0	0
T60	0	15372	0	0
T61	0	24031	0	0
T83	160761	0	0	0
T86	0	11674	0	0
T91	0	7296	0	0
T92	0	6453	0	0
T93	0	13387	0	0
T94	0	14490	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702764201	111566	0	0
T13	203957	2414	0	0
T14	129112	0	0	0
T29	157686	0	0	0
T30	172312	0	0	0
T31	12607	0	0	0
T38	713673	0	0	0
T45	0	19078	0	0
T46	0	750	0	0
T50	999460	0	0	0
T51	920271	0	0	0
T52	727200	0	0	0
T60	0	13419	0	0
T61	0	21310	0	0
T83	160761	0	0	0
T86	0	10447	0	0
T91	0	6303	0	0
T92	0	5698	0	0
T93	0	11982	0	0
T94	0	13157	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702764201	110140	0	0
T13	203957	2322	0	0
T14	129112	0	0	0
T29	157686	0	0	0
T30	172312	0	0	0
T31	12607	0	0	0
T38	713673	0	0	0
T45	0	18231	0	0
T46	0	776	0	0
T50	999460	0	0	0
T51	920271	0	0	0
T52	727200	0	0	0
T60	0	13420	0	0
T61	0	21423	0	0
T83	160761	0	0	0
T86	0	10554	0	0
T91	0	6112	0	0
T92	0	5993	0	0
T93	0	11315	0	0
T94	0	12673	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702764201	127365	0	0
T13	203957	2683	0	0
T14	129112	0	0	0
T29	157686	0	0	0
T30	172312	0	0	0
T31	12607	0	0	0
T38	713673	0	0	0
T45	0	21771	0	0
T46	0	786	0	0
T50	999460	0	0	0
T51	920271	0	0	0
T52	727200	0	0	0
T60	0	15290	0	0
T61	0	24487	0	0
T83	160761	0	0	0
T86	0	11977	0	0
T91	0	7569	0	0
T92	0	6333	0	0
T93	0	13509	0	0
T94	0	14872	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702764201	110823	0	0
T13	203957	2406	0	0
T14	129112	0	0	0
T29	157686	0	0	0
T30	172312	0	0	0
T31	12607	0	0	0
T38	713673	0	0	0
T45	0	18499	0	0
T46	0	843	0	0
T50	999460	0	0	0
T51	920271	0	0	0
T52	727200	0	0	0
T60	0	13529	0	0
T61	0	21135	0	0
T83	160761	0	0	0
T86	0	10279	0	0
T91	0	5908	0	0
T92	0	5775	0	0
T93	0	11663	0	0
T94	0	13368	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702764201	125726	0	0
T13	203957	2714	0	0
T14	129112	0	0	0
T29	157686	0	0	0
T30	172312	0	0	0
T31	12607	0	0	0
T38	713673	0	0	0
T45	0	21775	0	0
T46	0	849	0	0
T50	999460	0	0	0
T51	920271	0	0	0
T52	727200	0	0	0
T60	0	14871	0	0
T61	0	23806	0	0
T83	160761	0	0	0
T86	0	11660	0	0
T91	0	7369	0	0
T92	0	6626	0	0
T93	0	13223	0	0
T94	0	15050	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702764201	110418	0	0
T13	203957	2397	0	0
T14	129112	0	0	0
T29	157686	0	0	0
T30	172312	0	0	0
T31	12607	0	0	0
T38	713673	0	0	0
T45	0	18276	0	0
T46	0	717	0	0
T50	999460	0	0	0
T51	920271	0	0	0
T52	727200	0	0	0
T60	0	13180	0	0
T61	0	21388	0	0
T83	160761	0	0	0
T86	0	10481	0	0
T91	0	6419	0	0
T92	0	5972	0	0
T93	0	11346	0	0
T94	0	13152	0	0