Module Definition
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Module : aon_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.56 96.15 66.67 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 92.56 96.15 66.67 100.00 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.56 96.15 66.67 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.16 99.25 93.67 100.00 98.40 99.51


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
aon_timer_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_aon_intr_flop 100.00 100.00 100.00
u_core 100.00 100.00 100.00 100.00
u_intr_hw 100.00 100.00 100.00 100.00
u_intr_sync 100.00 100.00 100.00
u_lc_sync_escalate_en 100.00 100.00 100.00 100.00
u_reg 97.90 99.26 93.96 100.00 98.30 98.00
u_sync_sleep_mode 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : aon_timer
Line No.TotalCoveredPercent
TOTAL262596.15
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN84100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20911100.00
CONT_ASSIGN21011100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN24111100.00
ALWAYS24433100.00
CONT_ASSIGN25111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
81 1 1
82 1 1
83 1 1
84 0 1
85 1 1
86 1 1
109 1 1
165 1 1
169 1 1
201 1 1
203 1 1
204 1 1
205 1 1
206 1 1
209 1 1
210 1 1
211 1 1
212 1 1
230 1 1
231 1 1
234 1 1
241 1 1
244 1 1
245 1 1
247 1 1
251 1 1


Cond Coverage for Module : aon_timer
TotalCoveredPercent
Conditions12866.67
Logical12866.67
Non-Logical00
Event00

 LINE       109
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       165
 EXPRESSION (aon_wkup_intr_set | aon_wdog_intr_set)
             --------1--------   --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T9,T12
10CoveredT1,T2,T3

 LINE       201
 EXPRESSION (reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe)
             -------------------1------------------   -----------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       241
 EXPRESSION (aon_rst_req_set | aon_rst_req_q)
             -------1-------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T9,T10
10CoveredT7,T9,T10

Toggle Coverage for Module : aon_timer
TotalCoveredPercent
Totals 35 35 100.00
Total Bits 356 356 100.00
Total Bits 0->1 178 178 100.00
Total Bits 1->0 178 178 100.00

Ports 35 35 100.00
Port Bits 356 356 100.00
Port Bits 0->1 178 178 100.00
Port Bits 1->0 178 178 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T7,T8,T9 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T7,T8,T9 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T2,T4,T7 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T7,T8,T10 Yes T7,T8,T10 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_i.a_address[31:0] Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T8,T13,T14 Yes T8,T13,T14 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T7,T8,T9 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T15,T16,T17 Yes T15,T16,T17 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T15,T16,T17 Yes T15,T16,T17 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T7,T8,T9 Yes T7,T9,T12 INPUT
intr_wkup_timer_expired_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_wdog_timer_bark_o Yes Yes T7,T9,T12 Yes T7,T9,T12 OUTPUT
nmi_wdog_timer_bark_o Yes Yes T7,T9,T12 Yes T7,T9,T12 OUTPUT
wkup_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
aon_timer_rst_req_o Yes Yes T7,T9,T12 Yes T7,T9,T10 OUTPUT
sleep_mode_i Yes Yes T1,T2,T3 Yes T7,T9,T12 INPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : aon_timer
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 244 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 244 if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : aon_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 686220661 685785079 0 0
FpvSecCmRegWeOnehotCheck_A 686220661 70 0 0
IntrWdogKnown_A 686220661 685785079 0 0
IntrWkupKnown_A 686220661 685785079 0 0
RstReqKnown_A 3309782 3254531 0 0
TlOAReadyKnown_A 686220661 685785079 0 0
TlODValidKnown_A 686220661 685785079 0 0
WkupReqKnown_A 3309782 3254531 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 686220661 685785079 0 0
T1 912165 912101 0 0
T2 783786 783709 0 0
T3 446683 446676 0 0
T4 291768 291760 0 0
T5 21218 21140 0 0
T6 9417 9359 0 0
T7 696046 695302 0 0
T8 265096 263648 0 0
T9 160431 160397 0 0
T10 11146 11080 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 686220661 70 0 0
T15 454047 10 0 0
T16 0 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T19 0 10 0 0
T20 131604 0 0 0
T21 41871 0 0 0
T22 17588 0 0 0
T23 421004 0 0 0
T24 41016 0 0 0
T25 12686 0 0 0
T26 509143 0 0 0
T27 45453 0 0 0
T28 720781 0 0 0

IntrWdogKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 686220661 685785079 0 0
T1 912165 912101 0 0
T2 783786 783709 0 0
T3 446683 446676 0 0
T4 291768 291760 0 0
T5 21218 21140 0 0
T6 9417 9359 0 0
T7 696046 695302 0 0
T8 265096 263648 0 0
T9 160431 160397 0 0
T10 11146 11080 0 0

IntrWkupKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 686220661 685785079 0 0
T1 912165 912101 0 0
T2 783786 783709 0 0
T3 446683 446676 0 0
T4 291768 291760 0 0
T5 21218 21140 0 0
T6 9417 9359 0 0
T7 696046 695302 0 0
T8 265096 263648 0 0
T9 160431 160397 0 0
T10 11146 11080 0 0

RstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3309782 3254531 0 0
T1 3647 3579 0 0
T2 6530 6433 0 0
T3 8932 8879 0 0
T4 6141 6068 0 0
T5 84 16 0 0
T6 109 24 0 0
T7 23200 22448 0 0
T8 5521 5397 0 0
T9 45837 45584 0 0
T10 87 18 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 686220661 685785079 0 0
T1 912165 912101 0 0
T2 783786 783709 0 0
T3 446683 446676 0 0
T4 291768 291760 0 0
T5 21218 21140 0 0
T6 9417 9359 0 0
T7 696046 695302 0 0
T8 265096 263648 0 0
T9 160431 160397 0 0
T10 11146 11080 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 686220661 685785079 0 0
T1 912165 912101 0 0
T2 783786 783709 0 0
T3 446683 446676 0 0
T4 291768 291760 0 0
T5 21218 21140 0 0
T6 9417 9359 0 0
T7 696046 695302 0 0
T8 265096 263648 0 0
T9 160431 160397 0 0
T10 11146 11080 0 0

WkupReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3309782 3254531 0 0
T1 3647 3579 0 0
T2 6530 6433 0 0
T3 8932 8879 0 0
T4 6141 6068 0 0
T5 84 16 0 0
T6 109 24 0 0
T7 23200 22448 0 0
T8 5521 5397 0 0
T9 45837 45584 0 0
T10 87 18 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%