Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	352012	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4317566	1		T1	14		T2	13		T3	18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1148370	1		T1	1		T2	1		T3	1
values[0x0]	1650855	1		T1	10		T2	8		T3	9
values[0x1]	1870353	1		T1	11		T2	11		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157010	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4512568	1		T1	16		T2	15		T3	20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18604	1		T4	150		T10	624		T11	208
valid_sources[0x01]	18072	1		T4	162		T8	5		T10	661
valid_sources[0x02]	19905	1		T4	180		T8	1		T10	576
valid_sources[0x03]	19292	1		T4	214		T8	6		T10	633
valid_sources[0x04]	18376	1		T4	174		T8	7		T10	689
valid_sources[0x05]	17893	1		T4	213		T8	1		T10	581
valid_sources[0x06]	17858	1		T4	144		T8	6		T10	649
valid_sources[0x07]	18471	1		T4	205		T8	2		T10	622
valid_sources[0x08]	17731	1		T4	201		T8	3		T10	669
valid_sources[0x09]	19377	1		T4	216		T8	1		T10	624
valid_sources[0x0a]	16034	1		T4	180		T8	4		T10	639
valid_sources[0x0b]	19627	1		T4	188		T10	644		T11	287
valid_sources[0x0c]	19587	1		T4	183		T8	1		T10	722
valid_sources[0x0d]	18479	1		T4	184		T8	2		T10	667
valid_sources[0x0e]	16666	1		T4	190		T8	1		T10	641
valid_sources[0x0f]	18749	1		T4	162		T8	4		T10	639
valid_sources[0x10]	18540	1		T2	2		T4	203		T10	666
valid_sources[0x11]	19111	1		T4	157		T9	320		T10	620
valid_sources[0x12]	18940	1		T4	188		T10	594		T11	281
valid_sources[0x13]	16610	1		T4	190		T10	679		T11	321
valid_sources[0x14]	17897	1		T4	174		T8	4		T10	599
valid_sources[0x15]	17691	1		T4	176		T10	590		T11	345
valid_sources[0x16]	19485	1		T4	172		T8	1		T10	643
valid_sources[0x17]	18011	1		T4	243		T8	1		T10	680
valid_sources[0x18]	17237	1		T4	195		T8	2		T10	634
valid_sources[0x19]	20782	1		T4	197		T8	3		T10	576
valid_sources[0x1a]	19502	1		T4	181		T8	2		T10	617
valid_sources[0x1b]	19144	1		T4	194		T10	560		T11	343
valid_sources[0x1c]	18965	1		T4	200		T6	4		T8	1
valid_sources[0x1d]	18119	1		T4	187		T10	677		T11	345
valid_sources[0x1e]	18615	1		T3	2		T4	186		T10	605
valid_sources[0x1f]	20209	1		T4	194		T10	641		T11	284
valid_sources[0x20]	18019	1		T4	174		T8	2		T10	656
valid_sources[0x21]	17003	1		T4	174		T8	4		T10	738
valid_sources[0x22]	17470	1		T4	158		T8	1		T10	602
valid_sources[0x23]	18199	1		T4	203		T8	5		T10	614
valid_sources[0x24]	17637	1		T4	207		T10	615		T11	356
valid_sources[0x25]	17576	1		T4	193		T10	618		T11	366
valid_sources[0x26]	16837	1		T4	205		T10	633		T11	321
valid_sources[0x27]	17732	1		T4	190		T10	630		T11	303
valid_sources[0x28]	19084	1		T4	173		T5	9		T10	690
valid_sources[0x29]	18701	1		T4	175		T8	1		T10	685
valid_sources[0x2a]	18238	1		T4	157		T8	1		T10	652
valid_sources[0x2b]	17811	1		T4	205		T8	1		T10	627
valid_sources[0x2c]	19355	1		T4	217		T10	602		T11	373
valid_sources[0x2d]	17666	1		T4	166		T10	608		T11	250
valid_sources[0x2e]	16119	1		T4	185		T10	621		T11	249
valid_sources[0x2f]	17412	1		T4	182		T10	600		T11	325
valid_sources[0x30]	18015	1		T4	133		T8	2		T10	623
valid_sources[0x31]	17709	1		T4	195		T10	674		T11	297
valid_sources[0x32]	18639	1		T4	202		T8	2		T10	657
valid_sources[0x33]	19003	1		T4	178		T8	2		T10	612
valid_sources[0x34]	17990	1		T4	133		T10	621		T11	364
valid_sources[0x35]	19061	1		T4	166		T10	625		T11	311
valid_sources[0x36]	18242	1		T4	206		T10	588		T11	371
valid_sources[0x37]	16067	1		T4	156		T8	2		T10	618
valid_sources[0x38]	19022	1		T4	174		T10	675		T11	380
valid_sources[0x39]	19495	1		T4	157		T8	2		T10	616
valid_sources[0x3a]	19055	1		T4	213		T10	613		T11	305
valid_sources[0x3b]	19515	1		T4	149		T10	623		T11	225
valid_sources[0x3c]	16847	1		T4	191		T10	658		T11	292
valid_sources[0x3d]	18027	1		T4	210		T10	670		T11	257
valid_sources[0x3e]	17672	1		T4	196		T10	628		T11	231
valid_sources[0x3f]	18391	1		T4	188		T8	3		T10	630
valid_sources[0x40]	16736	1		T4	191		T8	1		T10	610
valid_sources[0x41]	18131	1		T4	173		T8	4		T10	623
valid_sources[0x42]	17818	1		T4	184		T5	3		T8	3
valid_sources[0x43]	18088	1		T4	211		T10	659		T11	236
valid_sources[0x44]	18011	1		T4	165		T8	2		T10	666
valid_sources[0x45]	19604	1		T4	160		T8	1		T10	613
valid_sources[0x46]	18167	1		T4	193		T10	647		T11	361
valid_sources[0x47]	17412	1		T4	172		T8	3		T10	663
valid_sources[0x48]	17253	1		T4	199		T8	1		T10	628
valid_sources[0x49]	17382	1		T4	162		T8	3		T10	662
valid_sources[0x4a]	17790	1		T4	163		T8	5		T10	669
valid_sources[0x4b]	19305	1		T4	161		T5	7		T8	2
valid_sources[0x4c]	18207	1		T4	169		T8	3		T10	662
valid_sources[0x4d]	18783	1		T4	213		T8	2		T10	637
valid_sources[0x4e]	19067	1		T4	178		T10	651		T11	378
valid_sources[0x4f]	16827	1		T4	175		T8	1		T10	622
valid_sources[0x50]	17226	1		T4	183		T8	1		T10	613
valid_sources[0x51]	19746	1		T4	171		T8	3		T10	667
valid_sources[0x52]	19012	1		T4	174		T8	9		T10	614
valid_sources[0x53]	18873	1		T4	173		T8	1		T10	574
valid_sources[0x54]	18347	1		T4	155		T8	1		T10	606
valid_sources[0x55]	18320	1		T4	177		T8	2		T10	680
valid_sources[0x56]	18281	1		T4	143		T8	5		T10	618
valid_sources[0x57]	17412	1		T4	185		T10	649		T11	329
valid_sources[0x58]	16868	1		T4	187		T8	1		T10	627
valid_sources[0x59]	18595	1		T4	183		T8	3		T10	612
valid_sources[0x5a]	21355	1		T4	154		T8	1		T10	706
valid_sources[0x5b]	17939	1		T4	196		T8	2		T10	638
valid_sources[0x5c]	16584	1		T4	224		T8	2		T10	600
valid_sources[0x5d]	17690	1		T4	131		T8	1		T10	609
valid_sources[0x5e]	17105	1		T4	176		T10	684		T11	315
valid_sources[0x5f]	19296	1		T4	175		T10	621		T11	353
valid_sources[0x60]	18056	1		T4	168		T8	1		T10	674
valid_sources[0x61]	18029	1		T4	162		T10	651		T11	303
valid_sources[0x62]	19866	1		T4	165		T8	1		T10	643
valid_sources[0x63]	17603	1		T4	160		T10	605		T11	343
valid_sources[0x64]	19895	1		T4	180		T8	4		T10	607
valid_sources[0x65]	17686	1		T4	199		T10	632		T11	245
valid_sources[0x66]	17743	1		T4	170		T10	634		T11	274
valid_sources[0x67]	18350	1		T4	210		T8	2		T10	687
valid_sources[0x68]	17355	1		T4	200		T10	661		T11	230
valid_sources[0x69]	19528	1		T4	157		T8	1		T10	650
valid_sources[0x6a]	18095	1		T2	2		T4	175		T10	611
valid_sources[0x6b]	17677	1		T4	159		T8	1		T10	597
valid_sources[0x6c]	18351	1		T4	158		T10	647		T11	374
valid_sources[0x6d]	18890	1		T4	206		T8	2		T10	654
valid_sources[0x6e]	17607	1		T4	145		T10	579		T11	295
valid_sources[0x6f]	17540	1		T4	176		T8	1		T10	588
valid_sources[0x70]	16674	1		T4	158		T8	1		T10	637
valid_sources[0x71]	18686	1		T4	190		T8	3		T10	636
valid_sources[0x72]	19142	1		T4	179		T8	1		T10	652
valid_sources[0x73]	18221	1		T4	156		T10	549		T11	265
valid_sources[0x74]	18353	1		T4	175		T8	1		T10	700
valid_sources[0x75]	17780	1		T4	152		T8	2		T10	619
valid_sources[0x76]	19300	1		T4	151		T8	1		T10	641
valid_sources[0x77]	16098	1		T4	160		T8	5		T10	608
valid_sources[0x78]	17046	1		T4	156		T10	668		T11	290
valid_sources[0x79]	19237	1		T4	156		T10	619		T11	334
valid_sources[0x7a]	18536	1		T4	189		T8	1		T10	596
valid_sources[0x7b]	19608	1		T4	211		T8	1		T10	614
valid_sources[0x7c]	18351	1		T4	204		T10	607		T11	283
valid_sources[0x7d]	16331	1		T4	204		T8	3		T10	679
valid_sources[0x7e]	18011	1		T4	207		T8	3		T10	666
valid_sources[0x7f]	18604	1		T4	177		T8	1		T10	628
valid_sources[0x80]	16785	1		T4	196		T5	3		T10	608

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1077072

1

T4

10674

T6

1

T7

1

values[0x0]

all_enables

biggest_size

1620702

1

T1

9

T2

5

T3

8

values[0x1]

all_enables

biggest_size

1619792

1

T1

5

T2

8

T3

10