Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	810104474	5092408	0	0
wdog_bark_thold_rd_A	810104474	122290	0	0
wdog_bite_thold_rd_A	810104474	107758	0	0
wdog_ctrl_rd_A	810104474	106497	0	0
wdog_regwen_rd_A	810104474	121804	0	0
wkup_ctrl_rd_A	810104474	105686	0	0
wkup_thold_hi_rd_A	810104474	122251	0	0
wkup_thold_lo_rd_A	810104474	107302	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	810104474	5092408	0	0
T4	252843	50702	0	0
T5	37286	0	0	0
T6	52923	0	0	0
T7	7575	0	0	0
T8	204644	0	0	0
T9	191942	0	0	0
T10	718374	167704	0	0
T11	747461	87487	0	0
T12	142037	34818	0	0
T13	402505	108791	0	0
T35	0	132921	0	0
T36	0	73332	0	0
T40	0	124392	0	0
T41	0	132479	0	0
T42	0	47960	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	810104474	122290	0	0
T10	718374	16797	0	0
T11	747461	0	0	0
T12	142037	0	0	0
T13	402505	0	0	0
T14	43981	0	0	0
T15	398230	0	0	0
T21	0	10254	0	0
T30	12389	0	0	0
T34	471726	0	0	0
T41	0	13417	0	0
T43	22378	0	0	0
T44	40947	0	0	0
T67	0	16741	0	0
T83	0	4342	0	0
T84	0	4772	0	0
T85	0	8100	0	0
T86	0	2620	0	0
T87	0	6543	0	0
T88	0	13242	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	810104474	107758	0	0
T10	718374	14461	0	0
T11	747461	0	0	0
T12	142037	0	0	0
T13	402505	0	0	0
T14	43981	0	0	0
T15	398230	0	0	0
T21	0	9181	0	0
T30	12389	0	0	0
T34	471726	0	0	0
T41	0	11591	0	0
T43	22378	0	0	0
T44	40947	0	0	0
T67	0	14879	0	0
T83	0	4135	0	0
T84	0	4191	0	0
T85	0	7018	0	0
T86	0	2523	0	0
T87	0	5751	0	0
T88	0	11779	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	810104474	106497	0	0
T10	718374	15325	0	0
T11	747461	0	0	0
T12	142037	0	0	0
T13	402505	0	0	0
T14	43981	0	0	0
T15	398230	0	0	0
T21	0	8969	0	0
T30	12389	0	0	0
T34	471726	0	0	0
T41	0	11318	0	0
T43	22378	0	0	0
T44	40947	0	0	0
T67	0	14070	0	0
T83	0	3530	0	0
T84	0	4327	0	0
T85	0	6866	0	0
T86	0	2357	0	0
T87	0	5417	0	0
T88	0	11358	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	810104474	121804	0	0
T10	718374	16791	0	0
T11	747461	0	0	0
T12	142037	0	0	0
T13	402505	0	0	0
T14	43981	0	0	0
T15	398230	0	0	0
T21	0	10153	0	0
T30	12389	0	0	0
T34	471726	0	0	0
T41	0	13359	0	0
T43	22378	0	0	0
T44	40947	0	0	0
T67	0	16952	0	0
T83	0	4407	0	0
T84	0	4640	0	0
T85	0	7594	0	0
T86	0	2782	0	0
T87	0	6358	0	0
T88	0	13055	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	810104474	105686	0	0
T10	718374	14630	0	0
T11	747461	0	0	0
T12	142037	0	0	0
T13	402505	0	0	0
T14	43981	0	0	0
T15	398230	0	0	0
T21	0	9089	0	0
T30	12389	0	0	0
T34	471726	0	0	0
T41	0	11519	0	0
T43	22378	0	0	0
T44	40947	0	0	0
T67	0	14255	0	0
T83	0	4001	0	0
T84	0	4167	0	0
T85	0	6952	0	0
T86	0	2421	0	0
T87	0	5350	0	0
T88	0	11217	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	810104474	122251	0	0
T10	718374	17191	0	0
T11	747461	0	0	0
T12	142037	0	0	0
T13	402505	0	0	0
T14	43981	0	0	0
T15	398230	0	0	0
T21	0	10523	0	0
T30	12389	0	0	0
T34	471726	0	0	0
T41	0	12582	0	0
T43	22378	0	0	0
T44	40947	0	0	0
T67	0	17121	0	0
T83	0	4875	0	0
T84	0	4419	0	0
T85	0	8032	0	0
T86	0	2632	0	0
T87	0	6249	0	0
T88	0	12723	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	810104474	107302	0	0
T10	718374	14811	0	0
T11	747461	0	0	0
T12	142037	0	0	0
T13	402505	0	0	0
T14	43981	0	0	0
T15	398230	0	0	0
T21	0	9267	0	0
T30	12389	0	0	0
T34	471726	0	0	0
T41	0	11614	0	0
T43	22378	0	0	0
T44	40947	0	0	0
T67	0	14485	0	0
T83	0	4008	0	0
T84	0	4036	0	0
T85	0	7119	0	0
T86	0	2208	0	0
T87	0	5799	0	0
T88	0	11344	0	0