Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	692749921	4981157	0	0
wdog_bark_thold_rd_A	692749921	146169	0	0
wdog_bite_thold_rd_A	692749921	126129	0	0
wdog_ctrl_rd_A	692749921	126931	0	0
wdog_regwen_rd_A	692749921	146955	0	0
wkup_ctrl_rd_A	692749921	126863	0	0
wkup_thold_hi_rd_A	692749921	146176	0	0
wkup_thold_lo_rd_A	692749921	125719	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692749921	4981157	0	0
T1	957158	257947	0	0
T2	455243	0	0	0
T3	13114	0	0	0
T4	43120	0	0	0
T5	8706	0	0	0
T6	296186	0	0	0
T7	111849	40697	0	0
T8	38255	0	0	0
T9	253880	0	0	0
T10	810889	0	0	0
T12	0	102156	0	0
T13	0	134497	0	0
T24	0	78087	0	0
T32	0	115783	0	0
T42	0	172398	0	0
T43	0	222557	0	0
T44	0	61285	0	0
T45	0	91790	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692749921	146169	0	0
T12	453918	10699	0	0
T13	504789	0	0	0
T24	0	4164	0	0
T30	19019	0	0	0
T31	13167	0	0	0
T32	862664	0	0	0
T33	19881	0	0	0
T45	0	4856	0	0
T46	438844	0	0	0
T47	120726	0	0	0
T48	22981	0	0	0
T49	18219	0	0	0
T59	0	6192	0	0
T87	0	5636	0	0
T91	0	5717	0	0
T93	0	24247	0	0
T94	0	15617	0	0
T95	0	1767	0	0
T96	0	10219	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692749921	126129	0	0
T12	453918	9451	0	0
T13	504789	0	0	0
T24	0	3537	0	0
T30	19019	0	0	0
T31	13167	0	0	0
T32	862664	0	0	0
T33	19881	0	0	0
T45	0	4078	0	0
T46	438844	0	0	0
T47	120726	0	0	0
T48	22981	0	0	0
T49	18219	0	0	0
T59	0	5396	0	0
T87	0	4864	0	0
T91	0	4400	0	0
T93	0	21006	0	0
T94	0	13698	0	0
T95	0	1192	0	0
T96	0	9053	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692749921	126931	0	0
T12	453918	9234	0	0
T13	504789	0	0	0
T24	0	3572	0	0
T30	19019	0	0	0
T31	13167	0	0	0
T32	862664	0	0	0
T33	19881	0	0	0
T45	0	4207	0	0
T46	438844	0	0	0
T47	120726	0	0	0
T48	22981	0	0	0
T49	18219	0	0	0
T59	0	5085	0	0
T87	0	4921	0	0
T91	0	5135	0	0
T93	0	20560	0	0
T94	0	13665	0	0
T95	0	1281	0	0
T96	0	8884	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692749921	146955	0	0
T12	453918	10813	0	0
T13	504789	0	0	0
T24	0	4139	0	0
T30	19019	0	0	0
T31	13167	0	0	0
T32	862664	0	0	0
T33	19881	0	0	0
T45	0	4915	0	0
T46	438844	0	0	0
T47	120726	0	0	0
T48	22981	0	0	0
T49	18219	0	0	0
T59	0	6221	0	0
T87	0	5452	0	0
T91	0	5725	0	0
T93	0	23815	0	0
T94	0	15922	0	0
T95	0	1553	0	0
T96	0	10416	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692749921	126863	0	0
T12	453918	9269	0	0
T13	504789	0	0	0
T24	0	3310	0	0
T30	19019	0	0	0
T31	13167	0	0	0
T32	862664	0	0	0
T33	19881	0	0	0
T45	0	4371	0	0
T46	438844	0	0	0
T47	120726	0	0	0
T48	22981	0	0	0
T49	18219	0	0	0
T59	0	5306	0	0
T87	0	5008	0	0
T91	0	4840	0	0
T93	0	21440	0	0
T94	0	12814	0	0
T95	0	1292	0	0
T96	0	9357	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692749921	146176	0	0
T12	453918	10786	0	0
T13	504789	0	0	0
T24	0	3953	0	0
T30	19019	0	0	0
T31	13167	0	0	0
T32	862664	0	0	0
T33	19881	0	0	0
T45	0	5064	0	0
T46	438844	0	0	0
T47	120726	0	0	0
T48	22981	0	0	0
T49	18219	0	0	0
T59	0	6006	0	0
T87	0	5596	0	0
T91	0	5577	0	0
T93	0	24334	0	0
T94	0	15396	0	0
T95	0	1355	0	0
T96	0	9841	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692749921	125719	0	0
T12	453918	9141	0	0
T13	504789	0	0	0
T24	0	3071	0	0
T30	19019	0	0	0
T31	13167	0	0	0
T32	862664	0	0	0
T33	19881	0	0	0
T45	0	4160	0	0
T46	438844	0	0	0
T47	120726	0	0	0
T48	22981	0	0	0
T49	18219	0	0	0
T59	0	5086	0	0
T87	0	4987	0	0
T91	0	4840	0	0
T93	0	21071	0	0
T94	0	13397	0	0
T95	0	1628	0	0
T96	0	9192	0	0