Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	344657	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4216700	1		T1	208755		T2	13		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1122479	1		T1	55370		T2	1		T3	1
values[0x0]	1611158	1		T1	79472		T2	9		T3	8
values[0x1]	1827720	1		T1	91128		T2	10		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153612	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4407745	1		T1	218606		T2	15		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16677	1		T1	894		T7	158		T12	322
valid_sources[0x01]	16294	1		T1	901		T7	161		T12	332
valid_sources[0x02]	17500	1		T1	863		T7	122		T10	4
valid_sources[0x03]	17837	1		T1	865		T7	153		T12	377
valid_sources[0x04]	16619	1		T1	927		T3	2		T7	124
valid_sources[0x05]	17422	1		T1	936		T7	152		T10	5
valid_sources[0x06]	18410	1		T1	868		T7	136		T12	408
valid_sources[0x07]	17980	1		T1	906		T3	8		T7	119
valid_sources[0x08]	17344	1		T1	894		T7	165		T10	4
valid_sources[0x09]	17641	1		T1	876		T6	1		T7	146
valid_sources[0x0a]	17617	1		T1	814		T6	1		T7	122
valid_sources[0x0b]	16602	1		T1	881		T7	122		T10	1
valid_sources[0x0c]	16965	1		T1	930		T7	106		T12	371
valid_sources[0x0d]	17425	1		T1	878		T5	1		T7	150
valid_sources[0x0e]	18951	1		T1	879		T7	171		T12	353
valid_sources[0x0f]	17546	1		T1	893		T7	163		T12	360
valid_sources[0x10]	17008	1		T1	884		T5	1		T7	118
valid_sources[0x11]	16883	1		T1	867		T7	122		T10	4
valid_sources[0x12]	18365	1		T1	891		T7	105		T10	2
valid_sources[0x13]	17506	1		T1	898		T7	168		T10	1
valid_sources[0x14]	18797	1		T1	829		T6	1		T7	147
valid_sources[0x15]	16167	1		T1	878		T7	140		T12	374
valid_sources[0x16]	18856	1		T1	919		T7	150		T12	361
valid_sources[0x17]	17684	1		T1	923		T7	173		T12	405
valid_sources[0x18]	18496	1		T1	830		T7	142		T10	1
valid_sources[0x19]	19365	1		T1	911		T7	117		T10	1
valid_sources[0x1a]	17381	1		T1	851		T7	172		T10	1
valid_sources[0x1b]	17563	1		T1	898		T5	1		T7	189
valid_sources[0x1c]	16943	1		T1	885		T7	135		T12	425
valid_sources[0x1d]	17391	1		T1	889		T7	124		T10	1
valid_sources[0x1e]	17680	1		T1	844		T4	2		T7	108
valid_sources[0x1f]	17229	1		T1	986		T5	2		T7	170
valid_sources[0x20]	16839	1		T1	837		T7	110		T12	387
valid_sources[0x21]	15899	1		T1	864		T7	115		T10	1
valid_sources[0x22]	17665	1		T1	879		T7	148		T12	413
valid_sources[0x23]	17388	1		T1	897		T7	158		T10	4
valid_sources[0x24]	18430	1		T1	862		T4	2		T7	131
valid_sources[0x25]	17595	1		T1	919		T7	173		T10	1
valid_sources[0x26]	18938	1		T1	835		T7	161		T12	342
valid_sources[0x27]	18861	1		T1	887		T7	146		T12	375
valid_sources[0x28]	18369	1		T1	883		T7	103		T10	4
valid_sources[0x29]	16338	1		T1	924		T5	1		T7	153
valid_sources[0x2a]	17997	1		T1	907		T7	127		T8	5
valid_sources[0x2b]	17885	1		T1	890		T5	1		T7	151
valid_sources[0x2c]	18047	1		T1	871		T7	84		T12	396
valid_sources[0x2d]	18376	1		T1	799		T4	1		T7	167
valid_sources[0x2e]	17229	1		T1	869		T7	152		T12	405
valid_sources[0x2f]	18311	1		T1	920		T2	2		T7	164
valid_sources[0x30]	17273	1		T1	906		T7	158		T10	3
valid_sources[0x31]	18408	1		T1	875		T7	120		T9	2
valid_sources[0x32]	18801	1		T1	875		T7	115		T10	4
valid_sources[0x33]	17449	1		T1	950		T7	103		T12	311
valid_sources[0x34]	17323	1		T1	879		T7	158		T10	2
valid_sources[0x35]	15829	1		T1	908		T7	144		T12	403
valid_sources[0x36]	17767	1		T1	891		T7	159		T10	4
valid_sources[0x37]	17269	1		T1	909		T5	1		T7	147
valid_sources[0x38]	18072	1		T1	874		T7	146		T10	5
valid_sources[0x39]	17275	1		T1	848		T7	109		T12	362
valid_sources[0x3a]	17183	1		T1	837		T4	1		T7	147
valid_sources[0x3b]	17732	1		T1	896		T7	141		T10	3
valid_sources[0x3c]	18728	1		T1	912		T7	126		T12	360
valid_sources[0x3d]	16859	1		T1	914		T7	138		T12	388
valid_sources[0x3e]	18010	1		T1	922		T7	160		T10	1
valid_sources[0x3f]	18419	1		T1	883		T7	98		T10	2
valid_sources[0x40]	17137	1		T1	896		T7	161		T10	3
valid_sources[0x41]	17920	1		T1	896		T7	146		T12	400
valid_sources[0x42]	18237	1		T1	832		T7	115		T10	1
valid_sources[0x43]	17067	1		T1	921		T7	151		T12	381
valid_sources[0x44]	18321	1		T1	846		T7	172		T10	1
valid_sources[0x45]	18568	1		T1	872		T7	157		T10	2
valid_sources[0x46]	17349	1		T1	865		T7	129		T10	3
valid_sources[0x47]	18732	1		T1	880		T7	199		T12	353
valid_sources[0x48]	17134	1		T1	888		T7	119		T10	3
valid_sources[0x49]	16892	1		T1	888		T7	104		T12	346
valid_sources[0x4a]	16687	1		T1	873		T7	115		T10	1
valid_sources[0x4b]	18125	1		T1	904		T7	135		T12	379
valid_sources[0x4c]	18599	1		T1	877		T7	133		T10	1
valid_sources[0x4d]	16709	1		T1	829		T7	158		T10	1
valid_sources[0x4e]	16692	1		T1	912		T7	152		T10	4
valid_sources[0x4f]	17359	1		T1	889		T7	137		T9	10
valid_sources[0x50]	18240	1		T1	931		T7	132		T12	371
valid_sources[0x51]	18902	1		T1	883		T3	3		T4	1
valid_sources[0x52]	17578	1		T1	891		T4	1		T7	133
valid_sources[0x53]	18550	1		T1	866		T7	120		T12	355
valid_sources[0x54]	19383	1		T1	897		T6	1		T7	122
valid_sources[0x55]	19192	1		T1	867		T7	217		T12	414
valid_sources[0x56]	18992	1		T1	891		T4	1		T7	159
valid_sources[0x57]	17438	1		T1	915		T7	159		T10	4
valid_sources[0x58]	19549	1		T1	905		T7	141		T12	363
valid_sources[0x59]	18276	1		T1	871		T7	115		T12	359
valid_sources[0x5a]	17604	1		T1	830		T6	1		T7	123
valid_sources[0x5b]	19413	1		T1	890		T6	1		T7	138
valid_sources[0x5c]	17312	1		T1	885		T7	121		T11	9
valid_sources[0x5d]	19190	1		T1	805		T7	166		T9	5
valid_sources[0x5e]	18359	1		T1	871		T5	1		T7	180
valid_sources[0x5f]	16623	1		T1	859		T7	132		T12	384
valid_sources[0x60]	19737	1		T1	877		T4	1		T7	115
valid_sources[0x61]	16892	1		T1	956		T7	150		T10	2
valid_sources[0x62]	17404	1		T1	802		T7	150		T10	1
valid_sources[0x63]	17894	1		T1	819		T7	139		T12	383
valid_sources[0x64]	17027	1		T1	899		T6	1		T7	171
valid_sources[0x65]	18779	1		T1	877		T4	1		T7	132
valid_sources[0x66]	17421	1		T1	911		T7	144		T10	2
valid_sources[0x67]	18463	1		T1	908		T7	142		T10	1
valid_sources[0x68]	17816	1		T1	892		T7	140		T12	378
valid_sources[0x69]	17922	1		T1	832		T7	143		T12	336
valid_sources[0x6a]	16967	1		T1	903		T7	140		T10	3
valid_sources[0x6b]	19054	1		T1	929		T7	147		T12	369
valid_sources[0x6c]	17309	1		T1	885		T7	148		T12	373
valid_sources[0x6d]	19737	1		T1	858		T7	167		T8	6
valid_sources[0x6e]	17683	1		T1	891		T5	1		T7	136
valid_sources[0x6f]	18470	1		T1	865		T7	132		T12	355
valid_sources[0x70]	17662	1		T1	849		T7	135		T12	392
valid_sources[0x71]	16505	1		T1	882		T7	155		T10	3
valid_sources[0x72]	17759	1		T1	903		T7	150		T12	345
valid_sources[0x73]	18622	1		T1	900		T7	117		T10	1
valid_sources[0x74]	18191	1		T1	878		T6	2		T7	124
valid_sources[0x75]	19499	1		T1	930		T7	143		T12	361
valid_sources[0x76]	17741	1		T1	860		T7	147		T10	1
valid_sources[0x77]	18232	1		T1	891		T7	138		T10	1
valid_sources[0x78]	17892	1		T1	885		T7	147		T10	1
valid_sources[0x79]	18383	1		T1	888		T7	145		T10	3
valid_sources[0x7a]	16246	1		T1	974		T6	1		T7	169
valid_sources[0x7b]	16894	1		T1	889		T6	1		T7	168
valid_sources[0x7c]	17311	1		T1	840		T7	112		T12	379
valid_sources[0x7d]	17711	1		T1	922		T6	1		T7	134
valid_sources[0x7e]	17990	1		T1	881		T5	1		T7	153
valid_sources[0x7f]	17728	1		T1	857		T7	132		T10	1
valid_sources[0x80]	17994	1		T1	897		T7	161		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1052875

1

T1

52192

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1581722

1

T1

78173

T2

5

T3

5

values[0x1]

all_enables

biggest_size

1582103

1

T1

78390

T2

7

T3

9