Module Definition
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Module : prim_flop_2sync
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sync_sleep_mode
tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync
tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync
tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync
tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync
tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync
tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.prim_flop_2sync
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync
tb.dut.u_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync
tb.dut.u_intr_sync.g_sync.u_sync



Module Instance : tb.dut.u_sync_sleep_mode

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 66.67 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 gen_passthru.u_dst_to_src_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 gen_passthru.u_dst_to_src_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 gen_passthru.u_dst_to_src_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 50.00 100.00 100.00 gen_wr_req.u_dst_update_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 50.00 100.00 100.00 gen_wr_req.u_dst_update_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 50.00 100.00 100.00 gen_wr_req.u_dst_update_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 50.00 100.00 100.00 gen_wr_req.u_dst_update_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 gen_passthru.u_dst_to_src_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 gen_passthru.u_dst_to_src_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 gen_passthru.u_dst_to_src_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 50.00 100.00 100.00 gen_wr_req.u_dst_update_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 50.00 100.00 100.00 gen_wr_req.u_dst_update_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_src_to_dst_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 50.00 100.00 100.00 gen_wr_req.u_dst_update_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 50.00 100.00 100.00 gen_wr_req.u_dst_update_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_sync_escalate_en


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_intr_sync.g_sync.u_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00

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