Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	571059890	5749403	0	0
wdog_bark_thold_rd_A	571059890	78458	0	0
wdog_bite_thold_rd_A	571059890	68774	0	0
wdog_ctrl_rd_A	571059890	69415	0	0
wdog_regwen_rd_A	571059890	78593	0	0
wkup_ctrl_rd_A	571059890	67756	0	0
wkup_thold_hi_rd_A	571059890	77904	0	0
wkup_thold_lo_rd_A	571059890	67842	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571059890	5749403	0	0
T16	592379	129833	0	0
T17	106911	0	0	0
T19	270662	39747	0	0
T20	354450	89777	0	0
T35	0	56712	0	0
T43	0	99923	0	0
T44	0	157186	0	0
T45	0	91676	0	0
T46	0	292874	0	0
T47	0	184883	0	0
T48	0	52013	0	0
T49	11556	0	0	0
T50	43335	0	0	0
T51	57650	0	0	0
T52	437236	0	0	0
T53	471869	0	0	0
T54	218912	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571059890	78458	0	0
T16	592379	13146	0	0
T17	106911	0	0	0
T19	270662	3616	0	0
T20	354450	4493	0	0
T35	0	2854	0	0
T49	11556	0	0	0
T50	43335	0	0	0
T51	57650	0	0	0
T52	437236	0	0	0
T53	471869	0	0	0
T54	218912	0	0	0
T56	0	11436	0	0
T94	0	2438	0	0
T95	0	6282	0	0
T96	0	7174	0	0
T97	0	5061	0	0
T98	0	2199	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571059890	68774	0	0
T16	592379	12093	0	0
T17	106911	0	0	0
T19	270662	3009	0	0
T20	354450	4120	0	0
T35	0	2550	0	0
T49	11556	0	0	0
T50	43335	0	0	0
T51	57650	0	0	0
T52	437236	0	0	0
T53	471869	0	0	0
T54	218912	0	0	0
T56	0	10065	0	0
T94	0	2169	0	0
T95	0	5219	0	0
T96	0	6422	0	0
T97	0	4250	0	0
T98	0	2089	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571059890	69415	0	0
T16	592379	11841	0	0
T17	106911	0	0	0
T19	270662	3298	0	0
T20	354450	3969	0	0
T35	0	2484	0	0
T49	11556	0	0	0
T50	43335	0	0	0
T51	57650	0	0	0
T52	437236	0	0	0
T53	471869	0	0	0
T54	218912	0	0	0
T56	0	10449	0	0
T94	0	2399	0	0
T95	0	5197	0	0
T96	0	6383	0	0
T97	0	4359	0	0
T98	0	2191	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571059890	78593	0	0
T16	592379	13590	0	0
T17	106911	0	0	0
T19	270662	3522	0	0
T20	354450	4503	0	0
T35	0	3140	0	0
T49	11556	0	0	0
T50	43335	0	0	0
T51	57650	0	0	0
T52	437236	0	0	0
T53	471869	0	0	0
T54	218912	0	0	0
T56	0	11098	0	0
T94	0	2500	0	0
T95	0	6258	0	0
T96	0	6961	0	0
T97	0	5151	0	0
T98	0	2305	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571059890	67756	0	0
T16	592379	11536	0	0
T17	106911	0	0	0
T19	270662	3112	0	0
T20	354450	3807	0	0
T35	0	2524	0	0
T49	11556	0	0	0
T50	43335	0	0	0
T51	57650	0	0	0
T52	437236	0	0	0
T53	471869	0	0	0
T54	218912	0	0	0
T56	0	10196	0	0
T94	0	2192	0	0
T95	0	4910	0	0
T96	0	6476	0	0
T97	0	4399	0	0
T98	0	1876	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571059890	77904	0	0
T16	592379	13299	0	0
T17	106911	0	0	0
T19	270662	3517	0	0
T20	354450	4602	0	0
T35	0	3120	0	0
T49	11556	0	0	0
T50	43335	0	0	0
T51	57650	0	0	0
T52	437236	0	0	0
T53	471869	0	0	0
T54	218912	0	0	0
T56	0	11807	0	0
T94	0	2257	0	0
T95	0	5913	0	0
T96	0	7174	0	0
T97	0	4663	0	0
T98	0	2116	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571059890	67842	0	0
T16	592379	11591	0	0
T17	106911	0	0	0
T19	270662	3166	0	0
T20	354450	4147	0	0
T35	0	2546	0	0
T49	11556	0	0	0
T50	43335	0	0	0
T51	57650	0	0	0
T52	437236	0	0	0
T53	471869	0	0	0
T54	218912	0	0	0
T56	0	10105	0	0
T94	0	2036	0	0
T95	0	5239	0	0
T96	0	6229	0	0
T97	0	4276	0	0
T98	0	2027	0	0