Line Coverage for Module :
aon_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 26 | 26 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
CONT_ASSIGN | 169 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 205 | 1 | 1 | 100.00 |
CONT_ASSIGN | 206 | 1 | 1 | 100.00 |
CONT_ASSIGN | 209 | 1 | 1 | 100.00 |
CONT_ASSIGN | 210 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
ALWAYS | 244 | 3 | 3 | 100.00 |
CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
109 |
1 |
1 |
165 |
1 |
1 |
169 |
1 |
1 |
201 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
212 |
1 |
1 |
230 |
1 |
1 |
231 |
1 |
1 |
234 |
1 |
1 |
241 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
247 |
1 |
1 |
251 |
1 |
1 |
Cond Coverage for Module :
aon_timer
| Total | Covered | Percent |
Conditions | 12 | 8 | 66.67 |
Logical | 12 | 8 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 109
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 165
EXPRESSION (aon_wkup_intr_set | aon_wdog_intr_set)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
LINE 201
EXPRESSION (reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe)
-------------------1------------------ -----------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 241
EXPRESSION (aon_rst_req_set | aon_rst_req_q)
-------1------- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
Toggle Coverage for Module :
aon_timer
| Total | Covered | Percent |
Totals |
35 |
35 |
100.00 |
Total Bits |
356 |
356 |
100.00 |
Total Bits 0->1 |
178 |
178 |
100.00 |
Total Bits 1->0 |
178 |
178 |
100.00 |
| | | |
Ports |
35 |
35 |
100.00 |
Port Bits |
356 |
356 |
100.00 |
Port Bits 0->1 |
178 |
178 |
100.00 |
Port Bits 1->0 |
178 |
178 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
clk_aon_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T2,T3,T10 |
Yes |
T1,T2,T3 |
INPUT |
rst_aon_ni |
Yes |
Yes |
T2,T3,T10 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T7,T9 |
Yes |
T1,T7,T9 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T2,T6 |
Yes |
T1,T2,T6 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T16,T19,T20 |
Yes |
T16,T19,T20 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T2,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T21,T22,T23 |
Yes |
T21,T22,T23 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T21,T22,T23 |
Yes |
T21,T22,T23 |
OUTPUT |
lc_escalate_en_i[3:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T2,T3,T10 |
INPUT |
intr_wkup_timer_expired_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
intr_wdog_timer_bark_o |
Yes |
Yes |
T2,T3,T4 |
Yes |
T2,T3,T4 |
OUTPUT |
nmi_wdog_timer_bark_o |
Yes |
Yes |
T2,T3,T4 |
Yes |
T2,T3,T4 |
OUTPUT |
wkup_req_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aon_timer_rst_req_o |
Yes |
Yes |
T2,T3,T10 |
Yes |
T2,T3,T4 |
OUTPUT |
sleep_mode_i |
Yes |
Yes |
T2,T3,T5 |
Yes |
T2,T3,T10 |
INPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
aon_timer
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
244 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 244 if ((!rst_aon_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
aon_timer
Assertion Details
AlertsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555561324 |
554923636 |
0 |
0 |
T1 |
22270 |
22216 |
0 |
0 |
T2 |
828853 |
828160 |
0 |
0 |
T3 |
333148 |
333070 |
0 |
0 |
T4 |
8909 |
8846 |
0 |
0 |
T5 |
9959 |
9903 |
0 |
0 |
T6 |
114587 |
114578 |
0 |
0 |
T7 |
28103 |
28011 |
0 |
0 |
T8 |
33051 |
32982 |
0 |
0 |
T9 |
729261 |
729179 |
0 |
0 |
T10 |
449470 |
449421 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555561324 |
80 |
0 |
0 |
T21 |
198384 |
20 |
0 |
0 |
T22 |
0 |
20 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T25 |
0 |
10 |
0 |
0 |
T26 |
104539 |
0 |
0 |
0 |
T27 |
35679 |
0 |
0 |
0 |
T28 |
55592 |
0 |
0 |
0 |
T29 |
22139 |
0 |
0 |
0 |
T30 |
77547 |
0 |
0 |
0 |
T31 |
396104 |
0 |
0 |
0 |
T32 |
23536 |
0 |
0 |
0 |
T33 |
178825 |
0 |
0 |
0 |
T34 |
2957 |
0 |
0 |
0 |
IntrWdogKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555561324 |
554923636 |
0 |
0 |
T1 |
22270 |
22216 |
0 |
0 |
T2 |
828853 |
828160 |
0 |
0 |
T3 |
333148 |
333070 |
0 |
0 |
T4 |
8909 |
8846 |
0 |
0 |
T5 |
9959 |
9903 |
0 |
0 |
T6 |
114587 |
114578 |
0 |
0 |
T7 |
28103 |
28011 |
0 |
0 |
T8 |
33051 |
32982 |
0 |
0 |
T9 |
729261 |
729179 |
0 |
0 |
T10 |
449470 |
449421 |
0 |
0 |
IntrWkupKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555561324 |
554923636 |
0 |
0 |
T1 |
22270 |
22216 |
0 |
0 |
T2 |
828853 |
828160 |
0 |
0 |
T3 |
333148 |
333070 |
0 |
0 |
T4 |
8909 |
8846 |
0 |
0 |
T5 |
9959 |
9903 |
0 |
0 |
T6 |
114587 |
114578 |
0 |
0 |
T7 |
28103 |
28011 |
0 |
0 |
T8 |
33051 |
32982 |
0 |
0 |
T9 |
729261 |
729179 |
0 |
0 |
T10 |
449470 |
449421 |
0 |
0 |
RstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2733117 |
2673445 |
0 |
0 |
T1 |
89 |
19 |
0 |
0 |
T2 |
8287 |
7532 |
0 |
0 |
T3 |
13596 |
12901 |
0 |
0 |
T4 |
73 |
20 |
0 |
0 |
T5 |
85 |
23 |
0 |
0 |
T6 |
9166 |
9111 |
0 |
0 |
T7 |
113 |
19 |
0 |
0 |
T8 |
121 |
24 |
0 |
0 |
T9 |
6076 |
6013 |
0 |
0 |
T10 |
18344 |
17818 |
0 |
0 |
TlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555561324 |
554923636 |
0 |
0 |
T1 |
22270 |
22216 |
0 |
0 |
T2 |
828853 |
828160 |
0 |
0 |
T3 |
333148 |
333070 |
0 |
0 |
T4 |
8909 |
8846 |
0 |
0 |
T5 |
9959 |
9903 |
0 |
0 |
T6 |
114587 |
114578 |
0 |
0 |
T7 |
28103 |
28011 |
0 |
0 |
T8 |
33051 |
32982 |
0 |
0 |
T9 |
729261 |
729179 |
0 |
0 |
T10 |
449470 |
449421 |
0 |
0 |
TlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555561324 |
554923636 |
0 |
0 |
T1 |
22270 |
22216 |
0 |
0 |
T2 |
828853 |
828160 |
0 |
0 |
T3 |
333148 |
333070 |
0 |
0 |
T4 |
8909 |
8846 |
0 |
0 |
T5 |
9959 |
9903 |
0 |
0 |
T6 |
114587 |
114578 |
0 |
0 |
T7 |
28103 |
28011 |
0 |
0 |
T8 |
33051 |
32982 |
0 |
0 |
T9 |
729261 |
729179 |
0 |
0 |
T10 |
449470 |
449421 |
0 |
0 |
WkupReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2733117 |
2673445 |
0 |
0 |
T1 |
89 |
19 |
0 |
0 |
T2 |
8287 |
7532 |
0 |
0 |
T3 |
13596 |
12901 |
0 |
0 |
T4 |
73 |
20 |
0 |
0 |
T5 |
85 |
23 |
0 |
0 |
T6 |
9166 |
9111 |
0 |
0 |
T7 |
113 |
19 |
0 |
0 |
T8 |
121 |
24 |
0 |
0 |
T9 |
6076 |
6013 |
0 |
0 |
T10 |
18344 |
17818 |
0 |
0 |