Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	956249224	5641999	0	0
wdog_bark_thold_rd_A	956249224	108061	0	0
wdog_bite_thold_rd_A	956249224	95353	0	0
wdog_ctrl_rd_A	956249224	96535	0	0
wdog_regwen_rd_A	956249224	110484	0	0
wkup_ctrl_rd_A	956249224	96124	0	0
wkup_thold_hi_rd_A	956249224	109562	0	0
wkup_thold_lo_rd_A	956249224	95040	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956249224	5641999	0	0
T3	321392	72637	0	0
T4	11951	0	0	0
T5	516675	170917	0	0
T6	202574	0	0	0
T7	110976	248712	0	0
T8	18962	0	0	0
T9	10145	0	0	0
T10	174826	0	0	0
T11	156755	0	0	0
T12	106013	0	0	0
T14	0	56203	0	0
T31	0	216856	0	0
T33	0	78037	0	0
T34	0	122231	0	0
T40	0	130339	0	0
T41	0	45966	0	0
T42	0	149047	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956249224	108061	0	0
T31	871951	11658	0	0
T32	172750	0	0	0
T33	366242	7710	0	0
T34	344109	0	0	0
T35	150094	0	0	0
T40	561654	12435	0	0
T41	0	4450	0	0
T44	8964	0	0	0
T96	0	5074	0	0
T97	0	5826	0	0
T98	0	11660	0	0
T99	0	5764	0	0
T100	0	2492	0	0
T101	0	12419	0	0
T102	9786	0	0	0
T103	52748	0	0	0
T104	8649	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956249224	95353	0	0
T31	871951	9915	0	0
T32	172750	0	0	0
T33	366242	6966	0	0
T34	344109	0	0	0
T35	150094	0	0	0
T40	561654	10872	0	0
T41	0	3817	0	0
T44	8964	0	0	0
T96	0	4473	0	0
T97	0	5430	0	0
T98	0	10384	0	0
T99	0	5137	0	0
T100	0	1967	0	0
T101	0	11464	0	0
T102	9786	0	0	0
T103	52748	0	0	0
T104	8649	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956249224	96535	0	0
T31	871951	10651	0	0
T32	172750	0	0	0
T33	366242	6896	0	0
T34	344109	0	0	0
T35	150094	0	0	0
T40	561654	10923	0	0
T41	0	3899	0	0
T44	8964	0	0	0
T96	0	4004	0	0
T97	0	5381	0	0
T98	0	10112	0	0
T99	0	5057	0	0
T100	0	2271	0	0
T101	0	11322	0	0
T102	9786	0	0	0
T103	52748	0	0	0
T104	8649	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956249224	110484	0	0
T31	871951	11500	0	0
T32	172750	0	0	0
T33	366242	7853	0	0
T34	344109	0	0	0
T35	150094	0	0	0
T40	561654	12586	0	0
T41	0	4652	0	0
T44	8964	0	0	0
T96	0	4932	0	0
T97	0	6006	0	0
T98	0	12022	0	0
T99	0	5969	0	0
T100	0	2748	0	0
T101	0	13006	0	0
T102	9786	0	0	0
T103	52748	0	0	0
T104	8649	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956249224	96124	0	0
T31	871951	10781	0	0
T32	172750	0	0	0
T33	366242	6862	0	0
T34	344109	0	0	0
T35	150094	0	0	0
T40	561654	10863	0	0
T41	0	4222	0	0
T44	8964	0	0	0
T96	0	4216	0	0
T97	0	5276	0	0
T98	0	10513	0	0
T99	0	4958	0	0
T100	0	2143	0	0
T101	0	11133	0	0
T102	9786	0	0	0
T103	52748	0	0	0
T104	8649	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956249224	109562	0	0
T31	871951	12343	0	0
T32	172750	0	0	0
T33	366242	7712	0	0
T34	344109	0	0	0
T35	150094	0	0	0
T40	561654	12360	0	0
T41	0	4551	0	0
T44	8964	0	0	0
T96	0	5087	0	0
T97	0	6094	0	0
T98	0	11833	0	0
T99	0	5964	0	0
T100	0	2369	0	0
T101	0	12771	0	0
T102	9786	0	0	0
T103	52748	0	0	0
T104	8649	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956249224	95040	0	0
T31	871951	10233	0	0
T32	172750	0	0	0
T33	366242	7089	0	0
T34	344109	0	0	0
T35	150094	0	0	0
T40	561654	10442	0	0
T41	0	4125	0	0
T44	8964	0	0	0
T96	0	4105	0	0
T97	0	5495	0	0
T98	0	10150	0	0
T99	0	5111	0	0
T100	0	2312	0	0
T101	0	10995	0	0
T102	9786	0	0	0
T103	52748	0	0	0
T104	8649	0	0	0