Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	743124653	5982113	0	0
wdog_bark_thold_rd_A	743124653	112649	0	0
wdog_bite_thold_rd_A	743124653	98222	0	0
wdog_ctrl_rd_A	743124653	97026	0	0
wdog_regwen_rd_A	743124653	113317	0	0
wkup_ctrl_rd_A	743124653	98164	0	0
wkup_thold_hi_rd_A	743124653	112297	0	0
wkup_thold_lo_rd_A	743124653	97810	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743124653	5982113	0	0
T1	176507	42012	0	0
T2	425355	0	0	0
T3	121852	422882	0	0
T4	10124	0	0	0
T5	186348	0	0	0
T6	129887	0	0	0
T7	11501	0	0	0
T8	714724	0	0	0
T9	13901	0	0	0
T10	9646	0	0	0
T14	0	84191	0	0
T30	0	448246	0	0
T31	0	81452	0	0
T41	0	16397	0	0
T42	0	172495	0	0
T43	0	55586	0	0
T44	0	310183	0	0
T45	0	185319	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743124653	112649	0	0
T1	176507	4208	0	0
T2	425355	0	0	0
T3	121852	0	0	0
T4	10124	0	0	0
T5	186348	0	0	0
T6	129887	0	0	0
T7	11501	0	0	0
T8	714724	0	0	0
T9	13901	0	0	0
T10	9646	0	0	0
T14	0	8101	0	0
T22	0	4149	0	0
T31	0	8270	0	0
T41	0	979	0	0
T42	0	9897	0	0
T43	0	5809	0	0
T86	0	20301	0	0
T90	0	4162	0	0
T91	0	5812	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743124653	98222	0	0
T1	176507	3635	0	0
T2	425355	0	0	0
T3	121852	0	0	0
T4	10124	0	0	0
T5	186348	0	0	0
T6	129887	0	0	0
T7	11501	0	0	0
T8	714724	0	0	0
T9	13901	0	0	0
T10	9646	0	0	0
T14	0	7186	0	0
T22	0	3473	0	0
T31	0	7267	0	0
T41	0	799	0	0
T42	0	8384	0	0
T43	0	5053	0	0
T86	0	17619	0	0
T90	0	3766	0	0
T91	0	5338	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743124653	97026	0	0
T1	176507	3706	0	0
T2	425355	0	0	0
T3	121852	0	0	0
T4	10124	0	0	0
T5	186348	0	0	0
T6	129887	0	0	0
T7	11501	0	0	0
T8	714724	0	0	0
T9	13901	0	0	0
T10	9646	0	0	0
T14	0	6874	0	0
T22	0	3374	0	0
T31	0	6706	0	0
T41	0	967	0	0
T42	0	8439	0	0
T43	0	4958	0	0
T86	0	17907	0	0
T90	0	3585	0	0
T91	0	5367	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743124653	113317	0	0
T1	176507	4068	0	0
T2	425355	0	0	0
T3	121852	0	0	0
T4	10124	0	0	0
T5	186348	0	0	0
T6	129887	0	0	0
T7	11501	0	0	0
T8	714724	0	0	0
T9	13901	0	0	0
T10	9646	0	0	0
T14	0	8011	0	0
T22	0	3813	0	0
T31	0	8189	0	0
T41	0	1026	0	0
T42	0	9012	0	0
T43	0	5945	0	0
T86	0	21356	0	0
T90	0	4183	0	0
T91	0	5869	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743124653	98164	0	0
T1	176507	3867	0	0
T2	425355	0	0	0
T3	121852	0	0	0
T4	10124	0	0	0
T5	186348	0	0	0
T6	129887	0	0	0
T7	11501	0	0	0
T8	714724	0	0	0
T9	13901	0	0	0
T10	9646	0	0	0
T14	0	6784	0	0
T22	0	3620	0	0
T31	0	7294	0	0
T41	0	986	0	0
T42	0	8157	0	0
T43	0	4963	0	0
T86	0	18102	0	0
T90	0	3753	0	0
T91	0	5321	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743124653	112297	0	0
T1	176507	4396	0	0
T2	425355	0	0	0
T3	121852	0	0	0
T4	10124	0	0	0
T5	186348	0	0	0
T6	129887	0	0	0
T7	11501	0	0	0
T8	714724	0	0	0
T9	13901	0	0	0
T10	9646	0	0	0
T14	0	7827	0	0
T22	0	3834	0	0
T31	0	8427	0	0
T41	0	870	0	0
T42	0	9528	0	0
T43	0	5554	0	0
T86	0	20720	0	0
T90	0	4205	0	0
T91	0	6049	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743124653	97810	0	0
T1	176507	3710	0	0
T2	425355	0	0	0
T3	121852	0	0	0
T4	10124	0	0	0
T5	186348	0	0	0
T6	129887	0	0	0
T7	11501	0	0	0
T8	714724	0	0	0
T9	13901	0	0	0
T10	9646	0	0	0
T14	0	6743	0	0
T22	0	3362	0	0
T31	0	7380	0	0
T41	0	904	0	0
T42	0	8182	0	0
T43	0	4809	0	0
T86	0	17839	0	0
T90	0	3852	0	0
T91	0	5589	0	0