Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	433910	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5416435	1		T1	18		T2	260933		T3	246

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1437367	1		T1	1		T2	68704		T3	43
values[0x0]	2069604	1		T1	10		T2	99624		T3	151
values[0x1]	2343374	1		T1	11		T2	113161		T3	164

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	191468	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5658877	1		T1	18		T2	272739		T3	268

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22162	1		T2	1134		T5	374		T6	184
valid_sources[0x01]	22428	1		T2	1114		T3	3		T5	396
valid_sources[0x02]	23792	1		T2	1115		T3	1		T5	762
valid_sources[0x03]	23784	1		T2	1127		T5	553		T6	260
valid_sources[0x04]	23119	1		T2	1076		T3	3		T5	534
valid_sources[0x05]	22660	1		T2	1089		T3	3		T5	467
valid_sources[0x06]	23008	1		T2	1133		T3	1		T5	537
valid_sources[0x07]	22130	1		T2	1081		T5	537		T6	213
valid_sources[0x08]	21547	1		T2	1048		T5	652		T6	220
valid_sources[0x09]	22702	1		T2	1107		T5	610		T6	228
valid_sources[0x0a]	22458	1		T2	1116		T3	1		T5	565
valid_sources[0x0b]	22253	1		T2	1076		T5	654		T6	247
valid_sources[0x0c]	22913	1		T2	1078		T3	5		T5	719
valid_sources[0x0d]	23074	1		T2	1058		T5	422		T6	184
valid_sources[0x0e]	22832	1		T2	1085		T5	540		T6	232
valid_sources[0x0f]	21884	1		T2	1079		T3	1		T5	562
valid_sources[0x10]	21934	1		T2	1081		T5	498		T6	200
valid_sources[0x11]	22414	1		T2	1049		T3	9		T5	566
valid_sources[0x12]	22989	1		T2	1124		T3	7		T5	687
valid_sources[0x13]	22063	1		T2	1061		T5	614		T6	255
valid_sources[0x14]	22274	1		T2	1188		T5	514		T6	203
valid_sources[0x15]	21432	1		T2	1110		T5	441		T6	208
valid_sources[0x16]	21900	1		T1	1		T2	1031		T5	656
valid_sources[0x17]	22370	1		T2	1103		T5	480		T6	233
valid_sources[0x18]	22522	1		T2	1085		T5	802		T6	270
valid_sources[0x19]	23460	1		T2	1053		T3	1		T5	618
valid_sources[0x1a]	23229	1		T2	1129		T3	5		T5	781
valid_sources[0x1b]	22579	1		T2	1048		T3	10		T5	628
valid_sources[0x1c]	23874	1		T2	1126		T5	590		T6	222
valid_sources[0x1d]	23310	1		T2	1160		T5	556		T6	192
valid_sources[0x1e]	23064	1		T2	1117		T5	557		T6	182
valid_sources[0x1f]	20973	1		T2	1073		T5	468		T6	267
valid_sources[0x20]	23125	1		T2	1082		T5	738		T6	206
valid_sources[0x21]	25292	1		T2	1162		T5	517		T6	205
valid_sources[0x22]	22442	1		T2	1052		T5	701		T6	178
valid_sources[0x23]	24053	1		T2	1194		T5	470		T6	226
valid_sources[0x24]	22477	1		T2	1075		T5	714		T6	267
valid_sources[0x25]	22738	1		T2	1113		T3	2		T5	524
valid_sources[0x26]	23161	1		T2	1103		T3	2		T5	685
valid_sources[0x27]	21879	1		T2	1093		T5	766		T6	276
valid_sources[0x28]	22553	1		T2	1126		T3	1		T5	656
valid_sources[0x29]	22258	1		T2	1115		T5	492		T6	187
valid_sources[0x2a]	22862	1		T2	1151		T5	672		T6	257
valid_sources[0x2b]	21810	1		T2	1155		T5	661		T6	231
valid_sources[0x2c]	23688	1		T2	1046		T5	533		T6	249
valid_sources[0x2d]	23284	1		T2	1110		T5	559		T6	259
valid_sources[0x2e]	23216	1		T2	1101		T5	608		T6	239
valid_sources[0x2f]	22495	1		T1	1		T2	1079		T5	611
valid_sources[0x30]	23514	1		T2	1095		T3	2		T5	522
valid_sources[0x31]	20925	1		T1	1		T2	1085		T3	4
valid_sources[0x32]	22194	1		T2	1098		T5	649		T6	250
valid_sources[0x33]	23221	1		T2	1080		T3	1		T5	522
valid_sources[0x34]	21229	1		T2	1120		T5	589		T6	199
valid_sources[0x35]	22071	1		T2	1141		T5	730		T6	211
valid_sources[0x36]	23824	1		T2	1109		T5	400		T6	247
valid_sources[0x37]	22884	1		T2	1082		T5	567		T6	230
valid_sources[0x38]	23173	1		T2	1048		T3	2		T5	754
valid_sources[0x39]	21289	1		T2	1096		T3	3		T5	671
valid_sources[0x3a]	22417	1		T2	1126		T3	6		T5	430
valid_sources[0x3b]	26761	1		T2	1129		T3	6		T5	904
valid_sources[0x3c]	24570	1		T2	1075		T5	532		T6	184
valid_sources[0x3d]	24688	1		T2	1080		T5	718		T6	233
valid_sources[0x3e]	23324	1		T2	1103		T5	334		T6	258
valid_sources[0x3f]	21807	1		T2	1109		T3	6		T5	383
valid_sources[0x40]	22904	1		T2	1043		T5	749		T6	205
valid_sources[0x41]	24527	1		T2	1055		T5	567		T6	207
valid_sources[0x42]	21779	1		T2	1165		T3	2		T5	737
valid_sources[0x43]	22148	1		T2	1121		T5	525		T6	208
valid_sources[0x44]	22871	1		T2	1100		T5	459		T6	239
valid_sources[0x45]	21346	1		T2	1069		T3	14		T5	780
valid_sources[0x46]	21234	1		T1	1		T2	1141		T3	3
valid_sources[0x47]	23202	1		T2	1219		T3	1		T5	771
valid_sources[0x48]	23414	1		T1	1		T2	1117		T3	4
valid_sources[0x49]	23388	1		T1	1		T2	1097		T5	599
valid_sources[0x4a]	22989	1		T2	1076		T3	4		T5	617
valid_sources[0x4b]	23750	1		T2	1014		T5	539		T6	202
valid_sources[0x4c]	23988	1		T2	1105		T5	555		T6	317
valid_sources[0x4d]	23247	1		T2	1077		T5	573		T6	164
valid_sources[0x4e]	21163	1		T2	1154		T5	376		T6	214
valid_sources[0x4f]	22889	1		T2	1120		T3	9		T5	600
valid_sources[0x50]	21253	1		T2	1091		T5	679		T6	261
valid_sources[0x51]	23582	1		T1	1		T2	1130		T5	740
valid_sources[0x52]	22183	1		T2	1080		T3	1		T5	800
valid_sources[0x53]	22348	1		T2	1121		T3	1		T5	554
valid_sources[0x54]	21992	1		T2	1089		T5	461		T6	222
valid_sources[0x55]	22511	1		T2	1104		T5	519		T6	234
valid_sources[0x56]	22408	1		T2	1060		T5	466		T6	221
valid_sources[0x57]	22460	1		T2	1137		T3	9		T5	477
valid_sources[0x58]	21474	1		T2	1101		T5	500		T6	256
valid_sources[0x59]	24678	1		T2	1085		T5	540		T6	233
valid_sources[0x5a]	23168	1		T2	1038		T5	324		T6	232
valid_sources[0x5b]	23899	1		T2	1137		T5	756		T6	240
valid_sources[0x5c]	24256	1		T2	1125		T3	7		T5	666
valid_sources[0x5d]	24391	1		T2	1127		T3	12		T5	534
valid_sources[0x5e]	23287	1		T2	1032		T5	533		T6	216
valid_sources[0x5f]	21986	1		T2	1079		T3	3		T5	469
valid_sources[0x60]	24818	1		T2	1059		T5	534		T6	226
valid_sources[0x61]	21714	1		T2	1047		T5	351		T6	199
valid_sources[0x62]	22222	1		T2	1082		T5	874		T6	180
valid_sources[0x63]	22834	1		T2	1092		T3	8		T5	694
valid_sources[0x64]	22850	1		T2	1036		T5	804		T6	184
valid_sources[0x65]	23317	1		T2	1086		T3	6		T5	324
valid_sources[0x66]	23663	1		T2	1107		T3	3		T5	559
valid_sources[0x67]	22527	1		T2	1058		T3	4		T5	810
valid_sources[0x68]	24394	1		T2	1091		T3	13		T5	673
valid_sources[0x69]	24026	1		T2	1133		T5	697		T6	231
valid_sources[0x6a]	24124	1		T2	1184		T5	668		T6	309
valid_sources[0x6b]	22418	1		T2	1096		T5	577		T6	272
valid_sources[0x6c]	23373	1		T2	1125		T5	751		T6	210
valid_sources[0x6d]	23690	1		T2	1026		T5	644		T6	244
valid_sources[0x6e]	24241	1		T1	1		T2	1117		T3	4
valid_sources[0x6f]	22464	1		T2	1087		T3	3		T5	419
valid_sources[0x70]	22558	1		T2	1093		T5	468		T6	225
valid_sources[0x71]	23209	1		T2	1073		T3	1		T5	501
valid_sources[0x72]	21707	1		T2	1127		T5	527		T6	269
valid_sources[0x73]	23711	1		T2	1079		T5	602		T6	204
valid_sources[0x74]	21422	1		T2	1079		T5	362		T6	194
valid_sources[0x75]	22966	1		T2	1060		T3	5		T5	503
valid_sources[0x76]	21667	1		T1	1		T2	1055		T5	400
valid_sources[0x77]	22839	1		T2	1059		T5	598		T6	187
valid_sources[0x78]	21889	1		T2	1123		T3	3		T5	584
valid_sources[0x79]	20736	1		T2	1086		T3	7		T5	466
valid_sources[0x7a]	22415	1		T2	1033		T3	3		T5	600
valid_sources[0x7b]	23364	1		T2	1096		T3	2		T5	642
valid_sources[0x7c]	22063	1		T2	1144		T3	3		T5	530
valid_sources[0x7d]	20852	1		T2	1047		T5	358		T6	273
valid_sources[0x7e]	22631	1		T1	1		T2	1100		T5	558
valid_sources[0x7f]	21526	1		T2	1082		T5	493		T6	221
valid_sources[0x80]	22198	1		T2	1095		T5	547		T6	257

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1350516

1

T1

1

T2

64735

T3

15

values[0x0]

all_enables

biggest_size

2034302

1

T1

7

T2

98062

T3

112

values[0x1]

all_enables

biggest_size

2031617

1

T1

10

T2

98136

T3

119