Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	835588047	6413400	0	0
wdog_bark_thold_rd_A	835588047	95495	0	0
wdog_bite_thold_rd_A	835588047	84155	0	0
wdog_ctrl_rd_A	835588047	85387	0	0
wdog_regwen_rd_A	835588047	96897	0	0
wkup_ctrl_rd_A	835588047	86245	0	0
wkup_thold_hi_rd_A	835588047	95307	0	0
wkup_thold_lo_rd_A	835588047	84757	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	835588047	6413400	0	0
T2	875765	317105	0	0
T3	222011	0	0	0
T5	650162	170154	0	0
T6	249111	64599	0	0
T7	6771	0	0	0
T8	8942	0	0	0
T9	12796	0	0	0
T10	15147	0	0	0
T11	379542	0	0	0
T12	207780	0	0	0
T28	0	269853	0	0
T29	0	94993	0	0
T30	0	90094	0	0
T31	0	158475	0	0
T32	0	199559	0	0
T33	0	50695	0	0
T34	0	345578	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	835588047	95495	0	0
T29	431884	10481	0	0
T30	355287	0	0	0
T31	775564	0	0	0
T32	747282	0	0	0
T33	0	2329	0	0
T38	788110	0	0	0
T47	0	20167	0	0
T74	590405	0	0	0
T75	13559	0	0	0
T76	14959	0	0	0
T85	0	12450	0	0
T87	0	8780	0	0
T88	0	8143	0	0
T89	0	9039	0	0
T90	0	4098	0	0
T91	0	13303	0	0
T92	0	5876	0	0
T93	25819	0	0	0
T94	6946	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	835588047	84155	0	0
T29	431884	8873	0	0
T30	355287	0	0	0
T31	775564	0	0	0
T32	747282	0	0	0
T33	0	2058	0	0
T38	788110	0	0	0
T47	0	18131	0	0
T74	590405	0	0	0
T75	13559	0	0	0
T76	14959	0	0	0
T85	0	10994	0	0
T87	0	7436	0	0
T88	0	7572	0	0
T89	0	8410	0	0
T90	0	3181	0	0
T91	0	11501	0	0
T92	0	5225	0	0
T93	25819	0	0	0
T94	6946	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	835588047	85387	0	0
T29	431884	9384	0	0
T30	355287	0	0	0
T31	775564	0	0	0
T32	747282	0	0	0
T33	0	2116	0	0
T38	788110	0	0	0
T47	0	18553	0	0
T74	590405	0	0	0
T75	13559	0	0	0
T76	14959	0	0	0
T85	0	10980	0	0
T87	0	7720	0	0
T88	0	7204	0	0
T89	0	7851	0	0
T90	0	3425	0	0
T91	0	11708	0	0
T92	0	5575	0	0
T93	25819	0	0	0
T94	6946	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	835588047	96897	0	0
T29	431884	9741	0	0
T30	355287	0	0	0
T31	775564	0	0	0
T32	747282	0	0	0
T33	0	2467	0	0
T38	788110	0	0	0
T47	0	21620	0	0
T74	590405	0	0	0
T75	13559	0	0	0
T76	14959	0	0	0
T85	0	13082	0	0
T87	0	8537	0	0
T88	0	8064	0	0
T89	0	9564	0	0
T90	0	3775	0	0
T91	0	13006	0	0
T92	0	6077	0	0
T93	25819	0	0	0
T94	6946	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	835588047	86245	0	0
T29	431884	8693	0	0
T30	355287	0	0	0
T31	775564	0	0	0
T32	747282	0	0	0
T33	0	2210	0	0
T38	788110	0	0	0
T47	0	18675	0	0
T74	590405	0	0	0
T75	13559	0	0	0
T76	14959	0	0	0
T85	0	11525	0	0
T87	0	7883	0	0
T88	0	7576	0	0
T89	0	8607	0	0
T90	0	3150	0	0
T91	0	11463	0	0
T92	0	5593	0	0
T93	25819	0	0	0
T94	6946	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	835588047	95307	0	0
T29	431884	10388	0	0
T30	355287	0	0	0
T31	775564	0	0	0
T32	747282	0	0	0
T33	0	2380	0	0
T38	788110	0	0	0
T47	0	20061	0	0
T74	590405	0	0	0
T75	13559	0	0	0
T76	14959	0	0	0
T85	0	12563	0	0
T87	0	8473	0	0
T88	0	8416	0	0
T89	0	9255	0	0
T90	0	3879	0	0
T91	0	13005	0	0
T92	0	6157	0	0
T93	25819	0	0	0
T94	6946	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	835588047	84757	0	0
T29	431884	8764	0	0
T30	355287	0	0	0
T31	775564	0	0	0
T32	747282	0	0	0
T33	0	2315	0	0
T38	788110	0	0	0
T47	0	18462	0	0
T74	590405	0	0	0
T75	13559	0	0	0
T76	14959	0	0	0
T85	0	11480	0	0
T87	0	7545	0	0
T88	0	7145	0	0
T89	0	8008	0	0
T90	0	3145	0	0
T91	0	11548	0	0
T92	0	5615	0	0
T93	25819	0	0	0
T94	6946	0	0	0