Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	327342	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3925757	1		T1	101677		T2	12		T3	13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1045804	1		T1	26977		T2	1		T3	1
values[0x0]	1500757	1		T1	38791		T2	7		T3	12
values[0x1]	1706538	1		T1	44199		T2	10		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146014	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4107085	1		T1	106339		T2	13		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16620	1		T1	486		T5	141		T6	123
valid_sources[0x01]	15815	1		T1	411		T5	208		T6	76
valid_sources[0x02]	18023	1		T1	352		T4	1		T5	169
valid_sources[0x03]	16174	1		T1	340		T4	2		T5	85
valid_sources[0x04]	16789	1		T1	498		T4	1		T5	131
valid_sources[0x05]	16272	1		T1	385		T4	1		T5	261
valid_sources[0x06]	16054	1		T1	444		T5	130		T6	102
valid_sources[0x07]	16369	1		T1	477		T4	2		T5	412
valid_sources[0x08]	16629	1		T1	435		T4	2		T5	216
valid_sources[0x09]	16661	1		T1	508		T4	1		T5	371
valid_sources[0x0a]	16598	1		T1	491		T4	1		T5	88
valid_sources[0x0b]	18931	1		T1	448		T4	2		T5	268
valid_sources[0x0c]	16955	1		T1	430		T4	4		T5	109
valid_sources[0x0d]	15667	1		T1	464		T3	1		T5	150
valid_sources[0x0e]	15367	1		T1	456		T4	3		T5	263
valid_sources[0x0f]	16756	1		T1	351		T4	1		T5	131
valid_sources[0x10]	16528	1		T1	353		T4	2		T5	415
valid_sources[0x11]	16210	1		T1	438		T4	1		T5	250
valid_sources[0x12]	16511	1		T1	432		T4	8		T5	160
valid_sources[0x13]	17497	1		T1	359		T4	1		T5	308
valid_sources[0x14]	16521	1		T1	452		T4	1		T5	263
valid_sources[0x15]	17768	1		T1	324		T4	4		T5	226
valid_sources[0x16]	17209	1		T1	454		T5	240		T6	108
valid_sources[0x17]	16294	1		T1	443		T4	1		T5	210
valid_sources[0x18]	14876	1		T1	388		T5	196		T6	60
valid_sources[0x19]	16148	1		T1	350		T3	3		T4	1
valid_sources[0x1a]	16303	1		T1	530		T5	210		T6	102
valid_sources[0x1b]	16743	1		T1	395		T4	2		T5	89
valid_sources[0x1c]	15314	1		T1	447		T4	2		T5	68
valid_sources[0x1d]	17814	1		T1	360		T4	2		T5	131
valid_sources[0x1e]	16769	1		T1	423		T4	3		T5	151
valid_sources[0x1f]	16478	1		T1	451		T5	211		T6	146
valid_sources[0x20]	16013	1		T1	430		T5	116		T6	124
valid_sources[0x21]	16138	1		T1	410		T4	3		T5	422
valid_sources[0x22]	15524	1		T1	381		T4	2		T5	277
valid_sources[0x23]	16713	1		T1	356		T4	1		T5	267
valid_sources[0x24]	15421	1		T1	350		T4	2		T5	162
valid_sources[0x25]	17433	1		T1	430		T4	5		T5	326
valid_sources[0x26]	16965	1		T1	487		T4	1		T5	110
valid_sources[0x27]	15769	1		T1	444		T4	1		T5	110
valid_sources[0x28]	16464	1		T1	400		T4	2		T5	217
valid_sources[0x29]	16575	1		T1	495		T4	2		T5	589
valid_sources[0x2a]	16321	1		T1	478		T4	1		T5	218
valid_sources[0x2b]	16090	1		T1	407		T4	4		T5	131
valid_sources[0x2c]	15915	1		T1	459		T4	4		T5	121
valid_sources[0x2d]	15996	1		T1	501		T4	1		T5	117
valid_sources[0x2e]	17280	1		T1	409		T4	1		T5	90
valid_sources[0x2f]	16900	1		T1	409		T4	2		T5	187
valid_sources[0x30]	17335	1		T1	392		T5	247		T6	144
valid_sources[0x31]	16931	1		T1	423		T5	173		T6	109
valid_sources[0x32]	17342	1		T1	471		T5	254		T6	151
valid_sources[0x33]	17186	1		T1	457		T4	1		T5	149
valid_sources[0x34]	17090	1		T1	398		T4	1		T5	329
valid_sources[0x35]	17695	1		T1	520		T5	193		T6	121
valid_sources[0x36]	17168	1		T1	452		T4	3		T5	427
valid_sources[0x37]	16234	1		T1	345		T4	1		T5	241
valid_sources[0x38]	17247	1		T1	360		T5	197		T6	116
valid_sources[0x39]	16534	1		T1	487		T4	5		T5	181
valid_sources[0x3a]	16306	1		T1	574		T4	3		T5	105
valid_sources[0x3b]	16690	1		T1	399		T5	233		T6	103
valid_sources[0x3c]	16354	1		T1	449		T4	3		T5	372
valid_sources[0x3d]	16973	1		T1	408		T4	1		T5	28
valid_sources[0x3e]	16349	1		T1	494		T4	2		T5	205
valid_sources[0x3f]	15588	1		T1	415		T4	1		T5	414
valid_sources[0x40]	15837	1		T1	427		T4	1		T5	162
valid_sources[0x41]	17047	1		T1	551		T3	2		T5	273
valid_sources[0x42]	16883	1		T1	430		T4	2		T5	115
valid_sources[0x43]	16255	1		T1	401		T4	2		T5	251
valid_sources[0x44]	16879	1		T1	472		T4	1		T5	38
valid_sources[0x45]	17608	1		T1	550		T4	1		T5	348
valid_sources[0x46]	17368	1		T1	372		T4	5		T5	97
valid_sources[0x47]	17593	1		T1	364		T4	1		T5	258
valid_sources[0x48]	15197	1		T1	417		T4	3		T5	108
valid_sources[0x49]	17908	1		T1	411		T4	1		T5	609
valid_sources[0x4a]	16985	1		T1	412		T5	167		T6	84
valid_sources[0x4b]	16188	1		T1	521		T4	2		T5	251
valid_sources[0x4c]	16091	1		T1	452		T4	1		T5	273
valid_sources[0x4d]	17104	1		T1	330		T5	240		T6	75
valid_sources[0x4e]	15525	1		T1	375		T4	2		T5	152
valid_sources[0x4f]	17242	1		T1	459		T4	4		T5	178
valid_sources[0x50]	16176	1		T1	403		T4	5		T5	265
valid_sources[0x51]	16943	1		T1	377		T5	171		T6	132
valid_sources[0x52]	16269	1		T1	449		T4	2		T5	118
valid_sources[0x53]	17452	1		T1	433		T4	2		T5	153
valid_sources[0x54]	17217	1		T1	356		T4	1		T5	198
valid_sources[0x55]	16866	1		T1	490		T4	1		T5	321
valid_sources[0x56]	17245	1		T1	412		T4	1		T5	346
valid_sources[0x57]	17494	1		T1	537		T3	1		T4	2
valid_sources[0x58]	16398	1		T1	387		T4	2		T5	174
valid_sources[0x59]	16303	1		T1	392		T5	171		T6	124
valid_sources[0x5a]	15661	1		T1	446		T4	1		T5	92
valid_sources[0x5b]	15989	1		T1	405		T5	96		T6	93
valid_sources[0x5c]	17068	1		T1	401		T4	1		T5	197
valid_sources[0x5d]	17244	1		T1	399		T4	2		T5	120
valid_sources[0x5e]	16831	1		T1	390		T5	386		T6	117
valid_sources[0x5f]	17361	1		T1	350		T5	184		T6	136
valid_sources[0x60]	16683	1		T1	474		T4	2		T5	403
valid_sources[0x61]	16662	1		T1	330		T4	2		T5	165
valid_sources[0x62]	17441	1		T1	472		T4	1		T5	414
valid_sources[0x63]	16353	1		T1	379		T4	1		T5	38
valid_sources[0x64]	17037	1		T1	432		T4	1		T5	519
valid_sources[0x65]	16427	1		T1	454		T4	1		T5	329
valid_sources[0x66]	16291	1		T1	416		T4	2		T5	202
valid_sources[0x67]	17536	1		T1	496		T4	1		T5	142
valid_sources[0x68]	15888	1		T1	408		T4	2		T5	272
valid_sources[0x69]	15913	1		T1	346		T4	2		T5	350
valid_sources[0x6a]	17316	1		T1	559		T4	2		T5	286
valid_sources[0x6b]	17024	1		T1	449		T4	3		T5	174
valid_sources[0x6c]	17019	1		T1	448		T5	628		T6	125
valid_sources[0x6d]	16581	1		T1	367		T4	3		T5	256
valid_sources[0x6e]	16024	1		T1	453		T4	2		T5	267
valid_sources[0x6f]	16433	1		T1	410		T4	2		T5	270
valid_sources[0x70]	16578	1		T1	367		T4	4		T5	113
valid_sources[0x71]	17060	1		T1	478		T4	5		T5	29
valid_sources[0x72]	17015	1		T1	400		T4	2		T5	247
valid_sources[0x73]	16816	1		T1	502		T5	453		T6	83
valid_sources[0x74]	17731	1		T1	426		T4	2		T5	109
valid_sources[0x75]	17305	1		T1	337		T4	3		T5	254
valid_sources[0x76]	16194	1		T1	530		T4	2		T5	250
valid_sources[0x77]	16208	1		T1	425		T4	4		T5	48
valid_sources[0x78]	17126	1		T1	443		T5	291		T6	94
valid_sources[0x79]	16651	1		T1	481		T3	4		T4	2
valid_sources[0x7a]	16697	1		T1	436		T5	258		T6	96
valid_sources[0x7b]	17407	1		T1	478		T5	406		T6	85
valid_sources[0x7c]	16209	1		T1	437		T4	1		T5	247
valid_sources[0x7d]	15533	1		T1	460		T4	2		T5	177
valid_sources[0x7e]	16592	1		T1	486		T4	1		T5	224
valid_sources[0x7f]	16161	1		T1	431		T5	149		T6	99
valid_sources[0x80]	17459	1		T1	399		T4	1		T5	115

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

978847

1

T1

25329

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1473142

1

T1

38129

T2

6

T3

7

values[0x1]

all_enables

biggest_size

1473768

1

T1

38219

T2

5

T3

5