Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	769915983	4722791	0	0
wdog_bark_thold_rd_A	769915983	80294	0	0
wdog_bite_thold_rd_A	769915983	72271	0	0
wdog_ctrl_rd_A	769915983	71840	0	0
wdog_regwen_rd_A	769915983	82378	0	0
wkup_ctrl_rd_A	769915983	71225	0	0
wkup_thold_hi_rd_A	769915983	81572	0	0
wkup_thold_lo_rd_A	769915983	70607	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769915983	4722791	0	0
T1	465549	130744	0	0
T2	11763	0	0	0
T3	700862	0	0	0
T4	166877	0	0	0
T5	249678	67010	0	0
T6	808904	29738	0	0
T7	23435	0	0	0
T8	464112	123968	0	0
T9	37870	0	0	0
T10	56385	0	0	0
T13	0	131505	0	0
T31	0	115713	0	0
T32	0	41115	0	0
T40	0	110340	0	0
T41	0	103666	0	0
T42	0	123665	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769915983	80294	0	0
T28	0	5419	0	0
T41	439490	9497	0	0
T42	443460	0	0	0
T46	166585	0	0	0
T47	642858	0	0	0
T48	0	22676	0	0
T80	0	12106	0	0
T86	0	1405	0	0
T87	0	11107	0	0
T88	0	1312	0	0
T89	0	3632	0	0
T90	0	6231	0	0
T91	0	5892	0	0
T92	356190	0	0	0
T93	9383	0	0	0
T94	130079	0	0	0
T95	27237	0	0	0
T96	10956	0	0	0
T97	19141	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769915983	72271	0	0
T28	0	4963	0	0
T41	439490	9158	0	0
T42	443460	0	0	0
T46	166585	0	0	0
T47	642858	0	0	0
T48	0	19440	0	0
T80	0	10985	0	0
T86	0	1472	0	0
T87	0	9831	0	0
T88	0	1130	0	0
T89	0	3264	0	0
T90	0	5808	0	0
T91	0	5164	0	0
T92	356190	0	0	0
T93	9383	0	0	0
T94	130079	0	0	0
T95	27237	0	0	0
T96	10956	0	0	0
T97	19141	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769915983	71840	0	0
T28	0	5149	0	0
T41	439490	8678	0	0
T42	443460	0	0	0
T46	166585	0	0	0
T47	642858	0	0	0
T48	0	19928	0	0
T80	0	10493	0	0
T86	0	1210	0	0
T87	0	9740	0	0
T88	0	1154	0	0
T89	0	3293	0	0
T90	0	5501	0	0
T91	0	5376	0	0
T92	356190	0	0	0
T93	9383	0	0	0
T94	130079	0	0	0
T95	27237	0	0	0
T96	10956	0	0	0
T97	19141	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769915983	82378	0	0
T28	0	5579	0	0
T41	439490	9852	0	0
T42	443460	0	0	0
T46	166585	0	0	0
T47	642858	0	0	0
T48	0	22362	0	0
T80	0	12669	0	0
T86	0	1540	0	0
T87	0	11148	0	0
T88	0	1309	0	0
T89	0	3746	0	0
T90	0	6485	0	0
T91	0	5815	0	0
T92	356190	0	0	0
T93	9383	0	0	0
T94	130079	0	0	0
T95	27237	0	0	0
T96	10956	0	0	0
T97	19141	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769915983	71225	0	0
T28	0	4679	0	0
T41	439490	8993	0	0
T42	443460	0	0	0
T46	166585	0	0	0
T47	642858	0	0	0
T48	0	20013	0	0
T80	0	10720	0	0
T86	0	1280	0	0
T87	0	9598	0	0
T88	0	1135	0	0
T89	0	3297	0	0
T90	0	5262	0	0
T91	0	4818	0	0
T92	356190	0	0	0
T93	9383	0	0	0
T94	130079	0	0	0
T95	27237	0	0	0
T96	10956	0	0	0
T97	19141	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769915983	81572	0	0
T28	0	5366	0	0
T41	439490	10007	0	0
T42	443460	0	0	0
T46	166585	0	0	0
T47	642858	0	0	0
T48	0	22617	0	0
T80	0	12622	0	0
T86	0	1490	0	0
T87	0	11330	0	0
T88	0	1223	0	0
T89	0	3756	0	0
T90	0	6115	0	0
T91	0	5865	0	0
T92	356190	0	0	0
T93	9383	0	0	0
T94	130079	0	0	0
T95	27237	0	0	0
T96	10956	0	0	0
T97	19141	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769915983	70607	0	0
T28	0	4800	0	0
T41	439490	8798	0	0
T42	443460	0	0	0
T46	166585	0	0	0
T47	642858	0	0	0
T48	0	19230	0	0
T80	0	10755	0	0
T86	0	1358	0	0
T87	0	9800	0	0
T88	0	1139	0	0
T89	0	3161	0	0
T90	0	5295	0	0
T91	0	5142	0	0
T92	356190	0	0	0
T93	9383	0	0	0
T94	130079	0	0	0
T95	27237	0	0	0
T96	10956	0	0	0
T97	19141	0	0	0