Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45986	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	363484	1		T1	7307		T2	13		T3	5171

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	103491	1		T1	2046		T2	1		T3	1434
values[0x0]	144349	1		T1	2850		T2	8		T3	1974
values[0x1]	161630	1		T1	3215		T2	11		T3	2187

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27142	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	382328	1		T1	7676		T2	13		T3	5367

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1730	1		T1	37		T3	17		T6	2
valid_sources[0x01]	1392	1		T1	42		T3	22		T14	26
valid_sources[0x02]	1516	1		T1	37		T3	9		T14	37
valid_sources[0x03]	2066	1		T1	22		T3	32		T14	20
valid_sources[0x04]	1475	1		T1	39		T3	35		T6	4
valid_sources[0x05]	1259	1		T1	31		T3	19		T6	2
valid_sources[0x06]	2122	1		T1	41		T3	11		T5	1
valid_sources[0x07]	1485	1		T1	28		T3	27		T18	5
valid_sources[0x08]	1527	1		T1	34		T3	45		T14	13
valid_sources[0x09]	1361	1		T1	39		T3	12		T4	3
valid_sources[0x0a]	1380	1		T1	35		T3	24		T6	1
valid_sources[0x0b]	1499	1		T1	33		T3	3		T18	1
valid_sources[0x0c]	1275	1		T1	31		T3	8		T4	3
valid_sources[0x0d]	1128	1		T1	22		T3	11		T14	31
valid_sources[0x0e]	1416	1		T1	28		T3	36		T5	1
valid_sources[0x0f]	1503	1		T1	30		T3	33		T6	2
valid_sources[0x10]	1864	1		T1	32		T2	2		T3	9
valid_sources[0x11]	1744	1		T1	33		T3	24		T5	1
valid_sources[0x12]	1269	1		T1	30		T3	16		T14	27
valid_sources[0x13]	1787	1		T1	41		T3	18		T14	36
valid_sources[0x14]	1512	1		T1	26		T3	20		T6	2
valid_sources[0x15]	1446	1		T1	27		T3	14		T14	24
valid_sources[0x16]	1474	1		T1	26		T3	39		T18	13
valid_sources[0x17]	1523	1		T1	47		T3	30		T14	31
valid_sources[0x18]	1595	1		T1	31		T3	10		T14	23
valid_sources[0x19]	1462	1		T1	43		T3	22		T6	2
valid_sources[0x1a]	1718	1		T1	34		T3	14		T6	1
valid_sources[0x1b]	1899	1		T1	27		T3	15		T14	26
valid_sources[0x1c]	1374	1		T1	38		T3	35		T14	29
valid_sources[0x1d]	1991	1		T1	29		T3	10		T4	2
valid_sources[0x1e]	1950	1		T1	33		T3	19		T6	2
valid_sources[0x1f]	1583	1		T1	29		T3	19		T6	1
valid_sources[0x20]	1901	1		T1	23		T3	16		T18	4
valid_sources[0x21]	1558	1		T1	27		T3	16		T6	1
valid_sources[0x22]	2029	1		T1	41		T3	21		T4	5
valid_sources[0x23]	1738	1		T1	33		T2	1		T3	12
valid_sources[0x24]	1751	1		T1	34		T3	4		T6	5
valid_sources[0x25]	1356	1		T1	39		T3	20		T6	1
valid_sources[0x26]	1610	1		T1	32		T3	4		T6	2
valid_sources[0x27]	1748	1		T1	23		T3	33		T6	2
valid_sources[0x28]	1765	1		T1	31		T3	20		T6	3
valid_sources[0x29]	1812	1		T1	33		T3	21		T6	3
valid_sources[0x2a]	1713	1		T1	23		T3	31		T6	2
valid_sources[0x2b]	1896	1		T1	30		T3	30		T14	36
valid_sources[0x2c]	1316	1		T1	28		T3	25		T6	2
valid_sources[0x2d]	1536	1		T1	32		T3	13		T10	3
valid_sources[0x2e]	1966	1		T1	25		T3	4		T6	2
valid_sources[0x2f]	1945	1		T1	29		T3	24		T6	1
valid_sources[0x30]	1467	1		T1	33		T3	30		T14	20
valid_sources[0x31]	1275	1		T1	26		T3	3		T18	6
valid_sources[0x32]	1418	1		T1	31		T3	6		T6	3
valid_sources[0x33]	1964	1		T1	27		T3	42		T6	2
valid_sources[0x34]	1490	1		T1	31		T3	14		T18	3
valid_sources[0x35]	1566	1		T1	24		T2	1		T3	32
valid_sources[0x36]	1125	1		T1	36		T3	21		T12	1
valid_sources[0x37]	1530	1		T1	29		T3	32		T6	1
valid_sources[0x38]	1496	1		T1	35		T3	17		T6	2
valid_sources[0x39]	1773	1		T1	31		T3	11		T14	24
valid_sources[0x3a]	1981	1		T1	23		T3	42		T18	1
valid_sources[0x3b]	1688	1		T1	36		T3	23		T6	3
valid_sources[0x3c]	1174	1		T1	30		T3	15		T10	2
valid_sources[0x3d]	1567	1		T1	25		T3	13		T12	1
valid_sources[0x3e]	1140	1		T1	22		T3	23		T5	1
valid_sources[0x3f]	1422	1		T1	32		T3	46		T5	1
valid_sources[0x40]	1379	1		T1	34		T3	7		T6	6
valid_sources[0x41]	1749	1		T1	29		T3	34		T11	2
valid_sources[0x42]	1670	1		T1	16		T3	36		T8	1
valid_sources[0x43]	1977	1		T1	27		T3	12		T6	1
valid_sources[0x44]	1636	1		T1	33		T3	22		T6	1
valid_sources[0x45]	1802	1		T1	36		T3	11		T6	2
valid_sources[0x46]	1619	1		T1	37		T2	1		T3	13
valid_sources[0x47]	1669	1		T1	34		T3	23		T18	5
valid_sources[0x48]	1295	1		T1	45		T2	1		T3	20
valid_sources[0x49]	1630	1		T1	35		T3	19		T14	42
valid_sources[0x4a]	1438	1		T1	28		T3	33		T6	3
valid_sources[0x4b]	1803	1		T1	26		T3	11		T5	1
valid_sources[0x4c]	1706	1		T1	35		T3	14		T6	1
valid_sources[0x4d]	1378	1		T1	24		T3	1		T14	54
valid_sources[0x4e]	1881	1		T1	28		T3	27		T10	1
valid_sources[0x4f]	1782	1		T1	41		T3	37		T6	2
valid_sources[0x50]	1924	1		T1	34		T3	29		T5	1
valid_sources[0x51]	1316	1		T1	31		T3	14		T6	1
valid_sources[0x52]	1571	1		T1	40		T3	7		T6	1
valid_sources[0x53]	1502	1		T1	31		T3	33		T6	1
valid_sources[0x54]	1437	1		T1	29		T3	14		T6	3
valid_sources[0x55]	1524	1		T1	21		T3	18		T6	1
valid_sources[0x56]	1671	1		T1	34		T3	5		T6	1
valid_sources[0x57]	1487	1		T1	41		T3	18		T5	1
valid_sources[0x58]	1591	1		T1	44		T3	26		T4	1
valid_sources[0x59]	1150	1		T1	17		T3	29		T6	1
valid_sources[0x5a]	1362	1		T1	24		T3	18		T12	1
valid_sources[0x5b]	1409	1		T1	41		T2	1		T3	15
valid_sources[0x5c]	1974	1		T1	37		T3	15		T6	1
valid_sources[0x5d]	1986	1		T1	37		T3	45		T14	25
valid_sources[0x5e]	1521	1		T1	31		T3	3		T6	1
valid_sources[0x5f]	1412	1		T1	30		T3	22		T6	1
valid_sources[0x60]	1862	1		T1	30		T3	21		T14	42
valid_sources[0x61]	1084	1		T1	28		T3	7		T14	15
valid_sources[0x62]	1549	1		T1	34		T3	24		T10	1
valid_sources[0x63]	1306	1		T1	34		T3	29		T6	1
valid_sources[0x64]	1574	1		T1	29		T3	20		T6	2
valid_sources[0x65]	1433	1		T1	34		T3	11		T14	37
valid_sources[0x66]	1634	1		T1	36		T3	33		T14	36
valid_sources[0x67]	1301	1		T1	27		T3	22		T14	40
valid_sources[0x68]	1559	1		T1	29		T3	80		T6	3
valid_sources[0x69]	1994	1		T1	39		T2	1		T3	36
valid_sources[0x6a]	1109	1		T1	30		T3	19		T18	3
valid_sources[0x6b]	1481	1		T1	26		T3	42		T14	27
valid_sources[0x6c]	1409	1		T1	29		T3	9		T14	20
valid_sources[0x6d]	1689	1		T1	30		T3	14		T6	5
valid_sources[0x6e]	1451	1		T1	41		T3	5		T11	1
valid_sources[0x6f]	1227	1		T1	26		T3	12		T14	28
valid_sources[0x70]	1316	1		T1	29		T3	14		T4	1
valid_sources[0x71]	1567	1		T1	41		T2	1		T3	49
valid_sources[0x72]	1364	1		T1	32		T3	32		T14	28
valid_sources[0x73]	2361	1		T1	41		T3	12		T18	34
valid_sources[0x74]	2424	1		T1	42		T3	5		T5	5
valid_sources[0x75]	1195	1		T1	37		T3	65		T14	28
valid_sources[0x76]	1773	1		T1	26		T3	30		T14	12
valid_sources[0x77]	1500	1		T1	34		T3	23		T14	24
valid_sources[0x78]	1231	1		T1	33		T3	25		T5	1
valid_sources[0x79]	1460	1		T1	33		T2	1		T3	34
valid_sources[0x7a]	2218	1		T1	32		T3	10		T6	3
valid_sources[0x7b]	1717	1		T1	34		T3	49		T6	2
valid_sources[0x7c]	1441	1		T1	25		T2	1		T3	4
valid_sources[0x7d]	1210	1		T1	21		T3	50		T14	21
valid_sources[0x7e]	1319	1		T1	33		T3	13		T6	1
valid_sources[0x7f]	1625	1		T1	25		T3	22		T6	1
valid_sources[0x80]	1349	1		T1	33		T3	27		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

90230

1

T1

1821

T3

1306

T4

1

values[0x0]

all_enables

biggest_size

136714

1

T1

2734

T2

7

T3

1929

values[0x1]

all_enables

biggest_size

136540

1

T1

2752

T2

6

T3

1936