Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	530622453	374438	0	0
wdog_bark_thold_rd_A	530622453	10490	0	0
wdog_bite_thold_rd_A	530622453	9720	0	0
wdog_ctrl_rd_A	530622453	9308	0	0
wdog_regwen_rd_A	530622453	11109	0	0
wkup_ctrl_rd_A	530622453	9117	0	0
wkup_thold_hi_rd_A	530622453	10348	0	0
wkup_thold_lo_rd_A	530622453	9080	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530622453	374438	0	0
T1	305641	7801	0	0
T2	239584	0	0	0
T3	293601	3900	0	0
T4	12161	0	0	0
T5	10721	0	0	0
T6	637681	0	0	0
T7	25770	0	0	0
T8	2916	0	0	0
T9	438749	0	0	0
T10	8985	0	0	0
T14	0	9329	0	0
T23	0	7865	0	0
T24	0	9122	0	0
T26	0	6276	0	0
T31	0	11402	0	0
T32	0	14349	0	0
T41	0	5471	0	0
T42	0	8496	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530622453	10490	0	0
T3	293601	595	0	0
T4	12161	0	0	0
T5	10721	0	0	0
T6	637681	0	0	0
T7	25770	0	0	0
T8	2916	0	0	0
T9	438749	0	0	0
T10	8985	0	0	0
T11	40510	0	0	0
T12	408981	0	0	0
T26	0	511	0	0
T31	0	680	0	0
T42	0	506	0	0
T73	0	344	0	0
T74	0	132	0	0
T75	0	500	0	0
T76	0	506	0	0
T77	0	564	0	0
T78	0	962	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530622453	9720	0	0
T3	293601	400	0	0
T4	12161	0	0	0
T5	10721	0	0	0
T6	637681	0	0	0
T7	25770	0	0	0
T8	2916	0	0	0
T9	438749	0	0	0
T10	8985	0	0	0
T11	40510	0	0	0
T12	408981	0	0	0
T26	0	501	0	0
T31	0	475	0	0
T42	0	537	0	0
T73	0	360	0	0
T74	0	171	0	0
T75	0	491	0	0
T76	0	500	0	0
T77	0	526	0	0
T78	0	907	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530622453	9308	0	0
T3	293601	453	0	0
T4	12161	0	0	0
T5	10721	0	0	0
T6	637681	0	0	0
T7	25770	0	0	0
T8	2916	0	0	0
T9	438749	0	0	0
T10	8985	0	0	0
T11	40510	0	0	0
T12	408981	0	0	0
T26	0	552	0	0
T31	0	482	0	0
T42	0	402	0	0
T73	0	354	0	0
T74	0	85	0	0
T75	0	474	0	0
T76	0	445	0	0
T77	0	386	0	0
T78	0	740	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530622453	11109	0	0
T3	293601	571	0	0
T4	12161	0	0	0
T5	10721	0	0	0
T6	637681	0	0	0
T7	25770	0	0	0
T8	2916	0	0	0
T9	438749	0	0	0
T10	8985	0	0	0
T11	40510	0	0	0
T12	408981	0	0	0
T26	0	644	0	0
T31	0	570	0	0
T42	0	514	0	0
T73	0	485	0	0
T74	0	180	0	0
T75	0	617	0	0
T76	0	489	0	0
T77	0	604	0	0
T78	0	961	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530622453	9117	0	0
T3	293601	473	0	0
T4	12161	0	0	0
T5	10721	0	0	0
T6	637681	0	0	0
T7	25770	0	0	0
T8	2916	0	0	0
T9	438749	0	0	0
T10	8985	0	0	0
T11	40510	0	0	0
T12	408981	0	0	0
T26	0	431	0	0
T31	0	477	0	0
T42	0	486	0	0
T73	0	361	0	0
T74	0	151	0	0
T75	0	315	0	0
T76	0	486	0	0
T77	0	454	0	0
T78	0	754	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530622453	10348	0	0
T3	293601	519	0	0
T4	12161	0	0	0
T5	10721	0	0	0
T6	637681	0	0	0
T7	25770	0	0	0
T8	2916	0	0	0
T9	438749	0	0	0
T10	8985	0	0	0
T11	40510	0	0	0
T12	408981	0	0	0
T26	0	527	0	0
T31	0	548	0	0
T42	0	538	0	0
T73	0	449	0	0
T74	0	149	0	0
T75	0	506	0	0
T76	0	481	0	0
T77	0	620	0	0
T78	0	909	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530622453	9080	0	0
T3	293601	493	0	0
T4	12161	0	0	0
T5	10721	0	0	0
T6	637681	0	0	0
T7	25770	0	0	0
T8	2916	0	0	0
T9	438749	0	0	0
T10	8985	0	0	0
T11	40510	0	0	0
T12	408981	0	0	0
T26	0	501	0	0
T31	0	560	0	0
T42	0	420	0	0
T73	0	283	0	0
T74	0	117	0	0
T75	0	405	0	0
T76	0	455	0	0
T77	0	497	0	0
T78	0	798	0	0