Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	410103577	351193	0	0
wdog_bark_thold_rd_A	410103577	9515	0	0
wdog_bite_thold_rd_A	410103577	8502	0	0
wdog_ctrl_rd_A	410103577	8700	0	0
wdog_regwen_rd_A	410103577	9969	0	0
wkup_ctrl_rd_A	410103577	8458	0	0
wkup_thold_hi_rd_A	410103577	9949	0	0
wkup_thold_lo_rd_A	410103577	8753	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410103577	351193	0	0
T4	329748	8182	0	0
T5	364384	0	0	0
T6	20458	0	0	0
T7	13161	0	0	0
T8	413139	0	0	0
T9	271921	0	0	0
T10	143546	5224	0	0
T12	0	5669	0	0
T29	0	2860	0	0
T32	0	7257	0	0
T33	22774	0	0	0
T42	0	16626	0	0
T43	0	4936	0	0
T44	0	10887	0	0
T45	0	9447	0	0
T46	0	3204	0	0
T47	13907	0	0	0
T48	21335	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410103577	9515	0	0
T4	329748	756	0	0
T5	364384	0	0	0
T6	20458	0	0	0
T7	13161	0	0	0
T8	413139	0	0	0
T9	271921	0	0	0
T10	143546	0	0	0
T29	0	163	0	0
T33	22774	0	0	0
T43	0	359	0	0
T46	0	197	0	0
T47	13907	0	0	0
T48	21335	0	0	0
T74	0	579	0	0
T75	0	332	0	0
T76	0	512	0	0
T77	0	423	0	0
T78	0	363	0	0
T79	0	547	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410103577	8502	0	0
T4	329748	638	0	0
T5	364384	0	0	0
T6	20458	0	0	0
T7	13161	0	0	0
T8	413139	0	0	0
T9	271921	0	0	0
T10	143546	0	0	0
T29	0	190	0	0
T33	22774	0	0	0
T43	0	332	0	0
T46	0	161	0	0
T47	13907	0	0	0
T48	21335	0	0	0
T74	0	528	0	0
T75	0	339	0	0
T76	0	486	0	0
T77	0	393	0	0
T78	0	343	0	0
T79	0	465	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410103577	8700	0	0
T4	329748	760	0	0
T5	364384	0	0	0
T6	20458	0	0	0
T7	13161	0	0	0
T8	413139	0	0	0
T9	271921	0	0	0
T10	143546	0	0	0
T29	0	166	0	0
T33	22774	0	0	0
T43	0	308	0	0
T46	0	137	0	0
T47	13907	0	0	0
T48	21335	0	0	0
T74	0	466	0	0
T75	0	288	0	0
T76	0	430	0	0
T77	0	484	0	0
T78	0	378	0	0
T79	0	555	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410103577	9969	0	0
T4	329748	761	0	0
T5	364384	0	0	0
T6	20458	0	0	0
T7	13161	0	0	0
T8	413139	0	0	0
T9	271921	0	0	0
T10	143546	0	0	0
T29	0	171	0	0
T33	22774	0	0	0
T43	0	313	0	0
T46	0	146	0	0
T47	13907	0	0	0
T48	21335	0	0	0
T74	0	609	0	0
T75	0	384	0	0
T76	0	609	0	0
T77	0	419	0	0
T78	0	340	0	0
T79	0	620	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410103577	8458	0	0
T4	329748	553	0	0
T5	364384	0	0	0
T6	20458	0	0	0
T7	13161	0	0	0
T8	413139	0	0	0
T9	271921	0	0	0
T10	143546	0	0	0
T29	0	143	0	0
T33	22774	0	0	0
T43	0	307	0	0
T46	0	119	0	0
T47	13907	0	0	0
T48	21335	0	0	0
T74	0	602	0	0
T75	0	240	0	0
T76	0	510	0	0
T77	0	367	0	0
T78	0	339	0	0
T79	0	513	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410103577	9949	0	0
T4	329748	836	0	0
T5	364384	0	0	0
T6	20458	0	0	0
T7	13161	0	0	0
T8	413139	0	0	0
T9	271921	0	0	0
T10	143546	0	0	0
T29	0	207	0	0
T33	22774	0	0	0
T43	0	391	0	0
T46	0	216	0	0
T47	13907	0	0	0
T48	21335	0	0	0
T74	0	623	0	0
T75	0	344	0	0
T76	0	523	0	0
T77	0	389	0	0
T78	0	363	0	0
T79	0	543	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410103577	8753	0	0
T4	329748	647	0	0
T5	364384	0	0	0
T6	20458	0	0	0
T7	13161	0	0	0
T8	413139	0	0	0
T9	271921	0	0	0
T10	143546	0	0	0
T29	0	94	0	0
T33	22774	0	0	0
T43	0	404	0	0
T46	0	161	0	0
T47	13907	0	0	0
T48	21335	0	0	0
T74	0	436	0	0
T75	0	350	0	0
T76	0	606	0	0
T77	0	331	0	0
T78	0	337	0	0
T79	0	535	0	0