Unified Coverage Report :: Module :: aon_timer

Module : aon_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	66.67	100.00		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.00	100.00	80.00	100.00		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00	100.00	80.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	99.33	95.61	100.00		98.40	99.51

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
aon_timer_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_aon_intr_flop	100.00	100.00				100.00
u_core	100.00	100.00	100.00			100.00
u_intr_hw	100.00	100.00				100.00	100.00
u_intr_sync	100.00	100.00				100.00
u_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_reg	98.26	99.26	95.74	100.00		98.30	98.00
u_sync_sleep_mode	100.00	100.00				100.00

Line Coverage for Module : aon_timer

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	244	3	3	100.00
CONT_ASSIGN	251	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
109	1	1
165	1	1
169	1	1
201	1	1
203	1	1
204	1	1
205	1	1
206	1	1
209	1	1
210	1	1
211	1	1
212	1	1
230	1	1
231	1	1
234	1	1
241	1	1
244	1	1
245	1	1
247	1	1
251	1	1

---

Cond Coverage for Module : aon_timer

	Total	Covered	Percent
Conditions	12	8	66.67
Logical	12	8	66.67
Non-Logical	0	0
Event	0	0

 LINE       109
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       165
 EXPRESSION (aon_wkup_intr_set | aon_wdog_intr_set)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       201
 EXPRESSION (reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe)
             -------------------1------------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       241
 EXPRESSION (aon_rst_req_set | aon_rst_req_q)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

---

Toggle Coverage for Module : aon_timer

	Total	Covered	Percent
Totals	35	35	100.00
Total Bits	356	356	100.00
Total Bits 0->1	178	178	100.00
Total Bits 1->0	178	178	100.00

Ports	35	35	100.00
Port Bits	356	356	100.00
Port Bits 0->1	178	178	100.00
Port Bits 1->0	178	178	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T10,T12	Yes	T4,T10,T12	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T5,T9	INPUT
intr_wkup_timer_expired_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
wkup_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sleep_mode_i	Yes	Yes	T2,T4,T5	Yes	T2,T5,T9	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : aon_timer

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	244	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	244	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : aon_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	397316473	397141134	0	0
FpvSecCmRegWeOnehotCheck_A	397316473	60	0	0
IntrWdogKnown_A	397316473	397141134	0	0
IntrWkupKnown_A	397316473	397141134	0	0
RstReqKnown_A	1703205	1647408	0	0
TlOAReadyKnown_A	397316473	397141134	0	0
TlODValidKnown_A	397316473	397141134	0	0
WkupReqKnown_A	1703205	1647408	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	60	0	0
T13	403697	10	0	0
T14	0	20	0	0
T15	0	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T18	141302	0	0	0
T19	424214	0	0	0
T20	198122	0	0	0
T21	194053	0	0	0
T22	416202	0	0	0
T23	12876	0	0	0
T24	124327	0	0	0
T25	14493	0	0	0
T26	233671	0	0	0

IntrWdogKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

IntrWkupKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

RstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1703205	1647408	0	0
T1	11916	11823	0	0
T2	12388	11431	0	0
T3	2767	2695	0	0
T4	10990	10890	0	0
T5	8281	7498	0	0
T6	80	22	0	0
T7	104	26	0	0
T8	3177	3104	0	0
T9	31989	31440	0	0
T10	1304	1203	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

WkupReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1703205	1647408	0	0
T1	11916	11823	0	0
T2	12388	11431	0	0
T3	2767	2695	0	0
T4	10990	10890	0	0
T5	8281	7498	0	0
T6	80	22	0	0
T7	104	26	0	0
T8	3177	3104	0	0
T9	31989	31440	0	0
T10	1304	1203	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	244	3	3	100.00
CONT_ASSIGN	251	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
109	1	1
165	1	1
169	1	1
201	1	1
203	1	1
204	1	1
205	1	1
206	1	1
209	1	1
210	1	1
211	1	1
212	1	1
230	1	1
231	1	1
234	1	1
241	1	1
244	1	1
245	1	1
247	1	1
251	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	10	8	80.00
Logical	10	8	80.00
Non-Logical	0	0
Event	0	0

 LINE       109
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       165
 EXPRESSION (aon_wkup_intr_set | aon_wdog_intr_set)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       201
 EXPRESSION (reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe)
             -------------------1------------------   -----------------2-----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       241
 EXPRESSION (aon_rst_req_set | aon_rst_req_q)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	35	35	100.00
Total Bits	356	356	100.00
Total Bits 0->1	178	178	100.00
Total Bits 1->0	178	178	100.00

Ports	35	35	100.00
Port Bits	356	356	100.00
Port Bits 0->1	178	178	100.00
Port Bits 1->0	178	178	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T10,T12	Yes	T4,T10,T12	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T5,T9	INPUT
intr_wkup_timer_expired_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
wkup_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sleep_mode_i	Yes	Yes	T2,T4,T5	Yes	T2,T5,T9	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	244	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	244	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	397316473	397141134	0	0
FpvSecCmRegWeOnehotCheck_A	397316473	60	0	0
IntrWdogKnown_A	397316473	397141134	0	0
IntrWkupKnown_A	397316473	397141134	0	0
RstReqKnown_A	1703205	1647408	0	0
TlOAReadyKnown_A	397316473	397141134	0	0
TlODValidKnown_A	397316473	397141134	0	0
WkupReqKnown_A	1703205	1647408	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	60	0	0
T13	403697	10	0	0
T14	0	20	0	0
T15	0	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T18	141302	0	0	0
T19	424214	0	0	0
T20	198122	0	0	0
T21	194053	0	0	0
T22	416202	0	0	0
T23	12876	0	0	0
T24	124327	0	0	0
T25	14493	0	0	0
T26	233671	0	0	0

IntrWdogKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

IntrWkupKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

RstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1703205	1647408	0	0
T1	11916	11823	0	0
T2	12388	11431	0	0
T3	2767	2695	0	0
T4	10990	10890	0	0
T5	8281	7498	0	0
T6	80	22	0	0
T7	104	26	0	0
T8	3177	3104	0	0
T9	31989	31440	0	0
T10	1304	1203	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397316473	397141134	0	0
T1	148966	148957	0	0
T2	167255	167147	0	0
T3	249137	249079	0	0
T4	329748	329355	0	0
T5	364384	364304	0	0
T6	20458	20359	0	0
T7	13161	13101	0	0
T8	413139	413069	0	0
T9	271921	271857	0	0
T10	143546	142903	0	0

WkupReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1703205	1647408	0	0
T1	11916	11823	0	0
T2	12388	11431	0	0
T3	2767	2695	0	0
T4	10990	10890	0	0
T5	8281	7498	0	0
T6	80	22	0	0
T7	104	26	0	0
T8	3177	3104	0	0
T9	31989	31440	0	0
T10	1304	1203	0	0