Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	517111313	275042	0	0
wdog_bark_thold_rd_A	517111313	3985	0	0
wdog_bite_thold_rd_A	517111313	3490	0	0
wdog_ctrl_rd_A	517111313	3723	0	0
wdog_regwen_rd_A	517111313	4138	0	0
wkup_ctrl_rd_A	517111313	3778	0	0
wkup_thold_hi_rd_A	517111313	3564	0	0
wkup_thold_lo_rd_A	517111313	3592	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517111313	275042	0	0
T20	67723	1867	0	0
T21	141701	2694	0	0
T22	0	1482	0	0
T30	0	2563	0	0
T32	194948	0	0	0
T34	44529	0	0	0
T35	41193	0	0	0
T43	0	3182	0	0
T44	0	4795	0	0
T45	0	6969	0	0
T46	0	6593	0	0
T47	0	5534	0	0
T48	0	6124	0	0
T49	33576	0	0	0
T50	521992	0	0	0
T51	10528	0	0	0
T52	11145	0	0	0
T53	15320	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517111313	3985	0	0
T22	163030	236	0	0
T27	220005	0	0	0
T28	871344	0	0	0
T30	201158	159	0	0
T36	0	54	0	0
T41	0	5	0	0
T43	145663	0	0	0
T78	0	937	0	0
T79	0	351	0	0
T80	0	366	0	0
T81	0	367	0	0
T82	0	554	0	0
T83	0	175	0	0
T84	25082	0	0	0
T85	260441	0	0	0
T86	8695	0	0	0
T87	614091	0	0	0
T88	667051	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517111313	3490	0	0
T22	163030	128	0	0
T27	220005	0	0	0
T28	871344	0	0	0
T30	201158	118	0	0
T36	0	41	0	0
T41	0	12	0	0
T43	145663	0	0	0
T78	0	775	0	0
T79	0	352	0	0
T80	0	332	0	0
T81	0	245	0	0
T82	0	521	0	0
T83	0	191	0	0
T84	25082	0	0	0
T85	260441	0	0	0
T86	8695	0	0	0
T87	614091	0	0	0
T88	667051	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517111313	3723	0	0
T22	163030	194	0	0
T27	220005	0	0	0
T28	871344	0	0	0
T30	201158	140	0	0
T36	0	60	0	0
T41	0	4	0	0
T43	145663	0	0	0
T78	0	943	0	0
T79	0	291	0	0
T80	0	352	0	0
T81	0	307	0	0
T82	0	510	0	0
T83	0	167	0	0
T84	25082	0	0	0
T85	260441	0	0	0
T86	8695	0	0	0
T87	614091	0	0	0
T88	667051	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517111313	4138	0	0
T22	163030	270	0	0
T27	220005	0	0	0
T28	871344	0	0	0
T30	201158	194	0	0
T36	0	46	0	0
T41	0	10	0	0
T43	145663	0	0	0
T78	0	947	0	0
T79	0	395	0	0
T80	0	524	0	0
T81	0	304	0	0
T82	0	490	0	0
T83	0	149	0	0
T84	25082	0	0	0
T85	260441	0	0	0
T86	8695	0	0	0
T87	614091	0	0	0
T88	667051	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517111313	3778	0	0
T22	163030	152	0	0
T27	220005	0	0	0
T28	871344	0	0	0
T30	201158	174	0	0
T36	0	66	0	0
T41	0	6	0	0
T43	145663	0	0	0
T78	0	725	0	0
T79	0	258	0	0
T80	0	486	0	0
T81	0	338	0	0
T82	0	574	0	0
T83	0	208	0	0
T84	25082	0	0	0
T85	260441	0	0	0
T86	8695	0	0	0
T87	614091	0	0	0
T88	667051	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517111313	3564	0	0
T22	163030	169	0	0
T27	220005	0	0	0
T28	871344	0	0	0
T30	201158	127	0	0
T36	0	32	0	0
T41	0	3	0	0
T43	145663	0	0	0
T78	0	797	0	0
T79	0	296	0	0
T80	0	442	0	0
T81	0	309	0	0
T82	0	567	0	0
T83	0	177	0	0
T84	25082	0	0	0
T85	260441	0	0	0
T86	8695	0	0	0
T87	614091	0	0	0
T88	667051	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517111313	3592	0	0
T22	163030	151	0	0
T27	220005	0	0	0
T28	871344	0	0	0
T30	201158	111	0	0
T36	0	27	0	0
T41	0	4	0	0
T43	145663	0	0	0
T78	0	793	0	0
T79	0	334	0	0
T80	0	380	0	0
T81	0	275	0	0
T82	0	437	0	0
T83	0	188	0	0
T84	25082	0	0	0
T85	260441	0	0	0
T86	8695	0	0	0
T87	614091	0	0	0
T88	667051	0	0	0