Line Coverage for Module :
aon_timer_reg_top
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 146 | 146 | 100.00 |
| ALWAYS | 70 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 209 | 1 | 1 | 100.00 |
| ALWAYS | 219 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
| ALWAYS | 257 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| ALWAYS | 298 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 328 | 1 | 1 | 100.00 |
| ALWAYS | 341 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 371 | 1 | 1 | 100.00 |
| ALWAYS | 383 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
| ALWAYS | 423 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
| ALWAYS | 462 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 490 | 1 | 1 | 100.00 |
| ALWAYS | 503 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 533 | 1 | 1 | 100.00 |
| ALWAYS | 546 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 576 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 583 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 597 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 714 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 744 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 803 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 862 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 893 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 923 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1010 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1025 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1041 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1046 | 1 | 1 | 100.00 |
| ALWAYS | 1077 | 15 | 15 | 100.00 |
| CONT_ASSIGN | 1094 | 1 | 1 | 100.00 |
| ALWAYS | 1098 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1124 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1152 | 1 | 1 | 100.00 |
| ALWAYS | 1157 | 15 | 15 | 100.00 |
| ALWAYS | 1176 | 18 | 18 | 100.00 |
| CONT_ASSIGN | 1238 | 1 | 1 | 100.00 |
| ALWAYS | 1240 | 12 | 12 | 100.00 |
| CONT_ASSIGN | 1285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1286 | 1 | 1 | 100.00 |
69 always_ff @(posedge clk_i or negedge rst_ni) begin
70 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
71 1/1 err_q <= '0;
Tests: T1 T2 T3
72 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
73 1/1 err_q <= 1'b1;
Tests: T11 T25 T26
74 end
MISSING_ELSE
75 end
76
77 // integrity error output is permanent and should be used for alert generation
78 // register errors are transactional
79 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
80
81 // outgoing integrity generation
82 tlul_pkg::tl_d2h_t tl_o_pre;
83 tlul_rsp_intg_gen #(
84 .EnableRspIntgGen(1),
85 .EnableDataIntgGen(1)
86 ) u_rsp_intg_gen (
87 .tl_i(tl_o_pre),
88 .tl_o(tl_o)
89 );
90
91 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
92 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
93
94 tlul_adapter_reg #(
95 .RegAw(AW),
96 .RegDw(DW),
97 .EnableDataIntgGen(0)
98 ) u_reg_if (
99 .clk_i (clk_i),
100 .rst_ni (rst_ni),
101
102 .tl_i (tl_reg_h2d),
103 .tl_o (tl_reg_d2h),
104
105 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
106 .intg_error_o(),
107
108 .we_o (reg_we),
109 .re_o (reg_re),
110 .addr_o (reg_addr),
111 .wdata_o (reg_wdata),
112 .be_o (reg_be),
113 .busy_i (reg_busy),
114 .rdata_i (reg_rdata),
115 .error_i (reg_error)
116 );
117
118 // cdc oversampling signals
119
120 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
121 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T2 T4 T5
122
123 // Define SW related signals
124 // Format: <reg>_<field>_{wd|we|qs}
125 // or <reg>_{wd|we|qs} if field == 1 or 0
126 logic alert_test_we;
127 logic alert_test_wd;
128 logic wkup_ctrl_we;
129 logic [12:0] wkup_ctrl_qs;
130 logic wkup_ctrl_busy;
131 logic wkup_thold_hi_we;
132 logic [31:0] wkup_thold_hi_qs;
133 logic wkup_thold_hi_busy;
134 logic wkup_thold_lo_we;
135 logic [31:0] wkup_thold_lo_qs;
136 logic wkup_thold_lo_busy;
137 logic wkup_count_hi_we;
138 logic [31:0] wkup_count_hi_qs;
139 logic wkup_count_hi_busy;
140 logic wkup_count_lo_we;
141 logic [31:0] wkup_count_lo_qs;
142 logic wkup_count_lo_busy;
143 logic wdog_regwen_we;
144 logic wdog_regwen_qs;
145 logic wdog_regwen_wd;
146 logic wdog_ctrl_we;
147 logic [1:0] wdog_ctrl_qs;
148 logic wdog_ctrl_busy;
149 logic wdog_bark_thold_we;
150 logic [31:0] wdog_bark_thold_qs;
151 logic wdog_bark_thold_busy;
152 logic wdog_bite_thold_we;
153 logic [31:0] wdog_bite_thold_qs;
154 logic wdog_bite_thold_busy;
155 logic wdog_count_we;
156 logic [31:0] wdog_count_qs;
157 logic wdog_count_busy;
158 logic intr_state_we;
159 logic intr_state_wkup_timer_expired_qs;
160 logic intr_state_wkup_timer_expired_wd;
161 logic intr_state_wdog_timer_bark_qs;
162 logic intr_state_wdog_timer_bark_wd;
163 logic intr_test_we;
164 logic intr_test_wkup_timer_expired_wd;
165 logic intr_test_wdog_timer_bark_wd;
166 logic wkup_cause_we;
167 logic [0:0] wkup_cause_qs;
168 logic wkup_cause_busy;
169 // Define register CDC handling.
170 // CDC handling is done on a per-reg instead of per-field boundary.
171
172 logic aon_wkup_ctrl_enable_qs_int;
173 logic [11:0] aon_wkup_ctrl_prescaler_qs_int;
174 logic [12:0] aon_wkup_ctrl_qs;
175 logic [12:0] aon_wkup_ctrl_wdata;
176 logic aon_wkup_ctrl_we;
177 logic unused_aon_wkup_ctrl_wdata;
178
179 always_comb begin
180 1/1 aon_wkup_ctrl_qs = 13'h0;
Tests: T1 T2 T3
181 1/1 aon_wkup_ctrl_qs[0] = aon_wkup_ctrl_enable_qs_int;
Tests: T1 T2 T3
182 1/1 aon_wkup_ctrl_qs[12:1] = aon_wkup_ctrl_prescaler_qs_int;
Tests: T1 T2 T3
183 end
184
185 prim_reg_cdc #(
186 .DataWidth(13),
187 .ResetVal(13'h0),
188 .BitMask(13'h1fff),
189 .DstWrReq(0)
190 ) u_wkup_ctrl_cdc (
191 .clk_src_i (clk_i),
192 .rst_src_ni (rst_ni),
193 .clk_dst_i (clk_aon_i),
194 .rst_dst_ni (rst_aon_ni),
195 .src_regwen_i ('0),
196 .src_we_i (wkup_ctrl_we),
197 .src_re_i ('0),
198 .src_wd_i (reg_wdata[12:0]),
199 .src_busy_o (wkup_ctrl_busy),
200 .src_qs_o (wkup_ctrl_qs), // for software read back
201 .dst_update_i ('0),
202 .dst_ds_i ('0),
203 .dst_qs_i (aon_wkup_ctrl_qs),
204 .dst_we_o (aon_wkup_ctrl_we),
205 .dst_re_o (),
206 .dst_regwen_o (),
207 .dst_wd_o (aon_wkup_ctrl_wdata)
208 );
209 1/1 assign unused_aon_wkup_ctrl_wdata =
Tests: T1 T2 T3
210 ^aon_wkup_ctrl_wdata;
211
212 logic [31:0] aon_wkup_thold_hi_qs_int;
213 logic [31:0] aon_wkup_thold_hi_qs;
214 logic [31:0] aon_wkup_thold_hi_wdata;
215 logic aon_wkup_thold_hi_we;
216 logic unused_aon_wkup_thold_hi_wdata;
217
218 always_comb begin
219 1/1 aon_wkup_thold_hi_qs = 32'h0;
Tests: T2 T4 T7
220 1/1 aon_wkup_thold_hi_qs = aon_wkup_thold_hi_qs_int;
Tests: T2 T4 T7
221 end
222
223 prim_reg_cdc #(
224 .DataWidth(32),
225 .ResetVal(32'h0),
226 .BitMask(32'hffffffff),
227 .DstWrReq(0)
228 ) u_wkup_thold_hi_cdc (
229 .clk_src_i (clk_i),
230 .rst_src_ni (rst_ni),
231 .clk_dst_i (clk_aon_i),
232 .rst_dst_ni (rst_aon_ni),
233 .src_regwen_i ('0),
234 .src_we_i (wkup_thold_hi_we),
235 .src_re_i ('0),
236 .src_wd_i (reg_wdata[31:0]),
237 .src_busy_o (wkup_thold_hi_busy),
238 .src_qs_o (wkup_thold_hi_qs), // for software read back
239 .dst_update_i ('0),
240 .dst_ds_i ('0),
241 .dst_qs_i (aon_wkup_thold_hi_qs),
242 .dst_we_o (aon_wkup_thold_hi_we),
243 .dst_re_o (),
244 .dst_regwen_o (),
245 .dst_wd_o (aon_wkup_thold_hi_wdata)
246 );
247 1/1 assign unused_aon_wkup_thold_hi_wdata =
Tests: T1 T2 T3
248 ^aon_wkup_thold_hi_wdata;
249
250 logic [31:0] aon_wkup_thold_lo_qs_int;
251 logic [31:0] aon_wkup_thold_lo_qs;
252 logic [31:0] aon_wkup_thold_lo_wdata;
253 logic aon_wkup_thold_lo_we;
254 logic unused_aon_wkup_thold_lo_wdata;
255
256 always_comb begin
257 1/1 aon_wkup_thold_lo_qs = 32'h0;
Tests: T1 T2 T3
258 1/1 aon_wkup_thold_lo_qs = aon_wkup_thold_lo_qs_int;
Tests: T1 T2 T3
259 end
260
261 prim_reg_cdc #(
262 .DataWidth(32),
263 .ResetVal(32'h0),
264 .BitMask(32'hffffffff),
265 .DstWrReq(0)
266 ) u_wkup_thold_lo_cdc (
267 .clk_src_i (clk_i),
268 .rst_src_ni (rst_ni),
269 .clk_dst_i (clk_aon_i),
270 .rst_dst_ni (rst_aon_ni),
271 .src_regwen_i ('0),
272 .src_we_i (wkup_thold_lo_we),
273 .src_re_i ('0),
274 .src_wd_i (reg_wdata[31:0]),
275 .src_busy_o (wkup_thold_lo_busy),
276 .src_qs_o (wkup_thold_lo_qs), // for software read back
277 .dst_update_i ('0),
278 .dst_ds_i ('0),
279 .dst_qs_i (aon_wkup_thold_lo_qs),
280 .dst_we_o (aon_wkup_thold_lo_we),
281 .dst_re_o (),
282 .dst_regwen_o (),
283 .dst_wd_o (aon_wkup_thold_lo_wdata)
284 );
285 1/1 assign unused_aon_wkup_thold_lo_wdata =
Tests: T1 T2 T3
286 ^aon_wkup_thold_lo_wdata;
287
288 logic [31:0] aon_wkup_count_hi_ds_int;
289 logic [31:0] aon_wkup_count_hi_qs_int;
290 logic [31:0] aon_wkup_count_hi_ds;
291 logic aon_wkup_count_hi_qe;
292 logic [31:0] aon_wkup_count_hi_qs;
293 logic [31:0] aon_wkup_count_hi_wdata;
294 logic aon_wkup_count_hi_we;
295 logic unused_aon_wkup_count_hi_wdata;
296
297 always_comb begin
298 1/1 aon_wkup_count_hi_qs = 32'h0;
Tests: T2 T4 T7
299 1/1 aon_wkup_count_hi_ds = 32'h0;
Tests: T2 T4 T7
300 1/1 aon_wkup_count_hi_ds = aon_wkup_count_hi_ds_int;
Tests: T2 T4 T7
301 1/1 aon_wkup_count_hi_qs = aon_wkup_count_hi_qs_int;
Tests: T2 T4 T7
302 end
303
304 prim_reg_cdc #(
305 .DataWidth(32),
306 .ResetVal(32'h0),
307 .BitMask(32'hffffffff),
308 .DstWrReq(1)
309 ) u_wkup_count_hi_cdc (
310 .clk_src_i (clk_i),
311 .rst_src_ni (rst_ni),
312 .clk_dst_i (clk_aon_i),
313 .rst_dst_ni (rst_aon_ni),
314 .src_regwen_i ('0),
315 .src_we_i (wkup_count_hi_we),
316 .src_re_i ('0),
317 .src_wd_i (reg_wdata[31:0]),
318 .src_busy_o (wkup_count_hi_busy),
319 .src_qs_o (wkup_count_hi_qs), // for software read back
320 .dst_update_i (aon_wkup_count_hi_qe),
321 .dst_ds_i (aon_wkup_count_hi_ds),
322 .dst_qs_i (aon_wkup_count_hi_qs),
323 .dst_we_o (aon_wkup_count_hi_we),
324 .dst_re_o (),
325 .dst_regwen_o (),
326 .dst_wd_o (aon_wkup_count_hi_wdata)
327 );
328 1/1 assign unused_aon_wkup_count_hi_wdata =
Tests: T1 T2 T3
329 ^aon_wkup_count_hi_wdata;
330
331 logic [31:0] aon_wkup_count_lo_ds_int;
332 logic [31:0] aon_wkup_count_lo_qs_int;
333 logic [31:0] aon_wkup_count_lo_ds;
334 logic aon_wkup_count_lo_qe;
335 logic [31:0] aon_wkup_count_lo_qs;
336 logic [31:0] aon_wkup_count_lo_wdata;
337 logic aon_wkup_count_lo_we;
338 logic unused_aon_wkup_count_lo_wdata;
339
340 always_comb begin
341 1/1 aon_wkup_count_lo_qs = 32'h0;
Tests: T1 T2 T3
342 1/1 aon_wkup_count_lo_ds = 32'h0;
Tests: T1 T2 T3
343 1/1 aon_wkup_count_lo_ds = aon_wkup_count_lo_ds_int;
Tests: T1 T2 T3
344 1/1 aon_wkup_count_lo_qs = aon_wkup_count_lo_qs_int;
Tests: T1 T2 T3
345 end
346
347 prim_reg_cdc #(
348 .DataWidth(32),
349 .ResetVal(32'h0),
350 .BitMask(32'hffffffff),
351 .DstWrReq(1)
352 ) u_wkup_count_lo_cdc (
353 .clk_src_i (clk_i),
354 .rst_src_ni (rst_ni),
355 .clk_dst_i (clk_aon_i),
356 .rst_dst_ni (rst_aon_ni),
357 .src_regwen_i ('0),
358 .src_we_i (wkup_count_lo_we),
359 .src_re_i ('0),
360 .src_wd_i (reg_wdata[31:0]),
361 .src_busy_o (wkup_count_lo_busy),
362 .src_qs_o (wkup_count_lo_qs), // for software read back
363 .dst_update_i (aon_wkup_count_lo_qe),
364 .dst_ds_i (aon_wkup_count_lo_ds),
365 .dst_qs_i (aon_wkup_count_lo_qs),
366 .dst_we_o (aon_wkup_count_lo_we),
367 .dst_re_o (),
368 .dst_regwen_o (),
369 .dst_wd_o (aon_wkup_count_lo_wdata)
370 );
371 1/1 assign unused_aon_wkup_count_lo_wdata =
Tests: T1 T2 T3
372 ^aon_wkup_count_lo_wdata;
373
374 logic aon_wdog_ctrl_enable_qs_int;
375 logic aon_wdog_ctrl_pause_in_sleep_qs_int;
376 logic [1:0] aon_wdog_ctrl_qs;
377 logic [1:0] aon_wdog_ctrl_wdata;
378 logic aon_wdog_ctrl_we;
379 logic unused_aon_wdog_ctrl_wdata;
380 logic aon_wdog_ctrl_regwen;
381
382 always_comb begin
383 1/1 aon_wdog_ctrl_qs = 2'h0;
Tests: T1 T2 T5
384 1/1 aon_wdog_ctrl_qs[0] = aon_wdog_ctrl_enable_qs_int;
Tests: T1 T2 T5
385 1/1 aon_wdog_ctrl_qs[1] = aon_wdog_ctrl_pause_in_sleep_qs_int;
Tests: T1 T2 T5
386 end
387
388 prim_reg_cdc #(
389 .DataWidth(2),
390 .ResetVal(2'h0),
391 .BitMask(2'h3),
392 .DstWrReq(0)
393 ) u_wdog_ctrl_cdc (
394 .clk_src_i (clk_i),
395 .rst_src_ni (rst_ni),
396 .clk_dst_i (clk_aon_i),
397 .rst_dst_ni (rst_aon_ni),
398 .src_regwen_i (wdog_regwen_qs),
399 .src_we_i (wdog_ctrl_we),
400 .src_re_i ('0),
401 .src_wd_i (reg_wdata[1:0]),
402 .src_busy_o (wdog_ctrl_busy),
403 .src_qs_o (wdog_ctrl_qs), // for software read back
404 .dst_update_i ('0),
405 .dst_ds_i ('0),
406 .dst_qs_i (aon_wdog_ctrl_qs),
407 .dst_we_o (aon_wdog_ctrl_we),
408 .dst_re_o (),
409 .dst_regwen_o (aon_wdog_ctrl_regwen),
410 .dst_wd_o (aon_wdog_ctrl_wdata)
411 );
412 1/1 assign unused_aon_wdog_ctrl_wdata =
Tests: T1 T2 T3
413 ^aon_wdog_ctrl_wdata;
414
415 logic [31:0] aon_wdog_bark_thold_qs_int;
416 logic [31:0] aon_wdog_bark_thold_qs;
417 logic [31:0] aon_wdog_bark_thold_wdata;
418 logic aon_wdog_bark_thold_we;
419 logic unused_aon_wdog_bark_thold_wdata;
420 logic aon_wdog_bark_thold_regwen;
421
422 always_comb begin
423 1/1 aon_wdog_bark_thold_qs = 32'h0;
Tests: T1 T2 T3
424 1/1 aon_wdog_bark_thold_qs = aon_wdog_bark_thold_qs_int;
Tests: T1 T2 T3
425 end
426
427 prim_reg_cdc #(
428 .DataWidth(32),
429 .ResetVal(32'h0),
430 .BitMask(32'hffffffff),
431 .DstWrReq(0)
432 ) u_wdog_bark_thold_cdc (
433 .clk_src_i (clk_i),
434 .rst_src_ni (rst_ni),
435 .clk_dst_i (clk_aon_i),
436 .rst_dst_ni (rst_aon_ni),
437 .src_regwen_i (wdog_regwen_qs),
438 .src_we_i (wdog_bark_thold_we),
439 .src_re_i ('0),
440 .src_wd_i (reg_wdata[31:0]),
441 .src_busy_o (wdog_bark_thold_busy),
442 .src_qs_o (wdog_bark_thold_qs), // for software read back
443 .dst_update_i ('0),
444 .dst_ds_i ('0),
445 .dst_qs_i (aon_wdog_bark_thold_qs),
446 .dst_we_o (aon_wdog_bark_thold_we),
447 .dst_re_o (),
448 .dst_regwen_o (aon_wdog_bark_thold_regwen),
449 .dst_wd_o (aon_wdog_bark_thold_wdata)
450 );
451 1/1 assign unused_aon_wdog_bark_thold_wdata =
Tests: T1 T2 T3
452 ^aon_wdog_bark_thold_wdata;
453
454 logic [31:0] aon_wdog_bite_thold_qs_int;
455 logic [31:0] aon_wdog_bite_thold_qs;
456 logic [31:0] aon_wdog_bite_thold_wdata;
457 logic aon_wdog_bite_thold_we;
458 logic unused_aon_wdog_bite_thold_wdata;
459 logic aon_wdog_bite_thold_regwen;
460
461 always_comb begin
462 1/1 aon_wdog_bite_thold_qs = 32'h0;
Tests: T1 T2 T3
463 1/1 aon_wdog_bite_thold_qs = aon_wdog_bite_thold_qs_int;
Tests: T1 T2 T3
464 end
465
466 prim_reg_cdc #(
467 .DataWidth(32),
468 .ResetVal(32'h0),
469 .BitMask(32'hffffffff),
470 .DstWrReq(0)
471 ) u_wdog_bite_thold_cdc (
472 .clk_src_i (clk_i),
473 .rst_src_ni (rst_ni),
474 .clk_dst_i (clk_aon_i),
475 .rst_dst_ni (rst_aon_ni),
476 .src_regwen_i (wdog_regwen_qs),
477 .src_we_i (wdog_bite_thold_we),
478 .src_re_i ('0),
479 .src_wd_i (reg_wdata[31:0]),
480 .src_busy_o (wdog_bite_thold_busy),
481 .src_qs_o (wdog_bite_thold_qs), // for software read back
482 .dst_update_i ('0),
483 .dst_ds_i ('0),
484 .dst_qs_i (aon_wdog_bite_thold_qs),
485 .dst_we_o (aon_wdog_bite_thold_we),
486 .dst_re_o (),
487 .dst_regwen_o (aon_wdog_bite_thold_regwen),
488 .dst_wd_o (aon_wdog_bite_thold_wdata)
489 );
490 1/1 assign unused_aon_wdog_bite_thold_wdata =
Tests: T1 T2 T3
491 ^aon_wdog_bite_thold_wdata;
492
493 logic [31:0] aon_wdog_count_ds_int;
494 logic [31:0] aon_wdog_count_qs_int;
495 logic [31:0] aon_wdog_count_ds;
496 logic aon_wdog_count_qe;
497 logic [31:0] aon_wdog_count_qs;
498 logic [31:0] aon_wdog_count_wdata;
499 logic aon_wdog_count_we;
500 logic unused_aon_wdog_count_wdata;
501
502 always_comb begin
503 1/1 aon_wdog_count_qs = 32'h0;
Tests: T1 T2 T3
504 1/1 aon_wdog_count_ds = 32'h0;
Tests: T1 T2 T3
505 1/1 aon_wdog_count_ds = aon_wdog_count_ds_int;
Tests: T1 T2 T3
506 1/1 aon_wdog_count_qs = aon_wdog_count_qs_int;
Tests: T1 T2 T3
507 end
508
509 prim_reg_cdc #(
510 .DataWidth(32),
511 .ResetVal(32'h0),
512 .BitMask(32'hffffffff),
513 .DstWrReq(1)
514 ) u_wdog_count_cdc (
515 .clk_src_i (clk_i),
516 .rst_src_ni (rst_ni),
517 .clk_dst_i (clk_aon_i),
518 .rst_dst_ni (rst_aon_ni),
519 .src_regwen_i ('0),
520 .src_we_i (wdog_count_we),
521 .src_re_i ('0),
522 .src_wd_i (reg_wdata[31:0]),
523 .src_busy_o (wdog_count_busy),
524 .src_qs_o (wdog_count_qs), // for software read back
525 .dst_update_i (aon_wdog_count_qe),
526 .dst_ds_i (aon_wdog_count_ds),
527 .dst_qs_i (aon_wdog_count_qs),
528 .dst_we_o (aon_wdog_count_we),
529 .dst_re_o (),
530 .dst_regwen_o (),
531 .dst_wd_o (aon_wdog_count_wdata)
532 );
533 1/1 assign unused_aon_wdog_count_wdata =
Tests: T1 T2 T3
534 ^aon_wdog_count_wdata;
535
536 logic aon_wkup_cause_ds_int;
537 logic aon_wkup_cause_qs_int;
538 logic [0:0] aon_wkup_cause_ds;
539 logic aon_wkup_cause_qe;
540 logic [0:0] aon_wkup_cause_qs;
541 logic [0:0] aon_wkup_cause_wdata;
542 logic aon_wkup_cause_we;
543 logic unused_aon_wkup_cause_wdata;
544
545 always_comb begin
546 1/1 aon_wkup_cause_qs = 1'h0;
Tests: T2 T3 T4
547 1/1 aon_wkup_cause_ds = 1'h0;
Tests: T2 T3 T4
548 1/1 aon_wkup_cause_ds = aon_wkup_cause_ds_int;
Tests: T2 T3 T4
549 1/1 aon_wkup_cause_qs = aon_wkup_cause_qs_int;
Tests: T2 T3 T4
550 end
551
552 prim_reg_cdc #(
553 .DataWidth(1),
554 .ResetVal(1'h0),
555 .BitMask(1'h1),
556 .DstWrReq(1)
557 ) u_wkup_cause_cdc (
558 .clk_src_i (clk_i),
559 .rst_src_ni (rst_ni),
560 .clk_dst_i (clk_aon_i),
561 .rst_dst_ni (rst_aon_ni),
562 .src_regwen_i ('0),
563 .src_we_i (wkup_cause_we),
564 .src_re_i ('0),
565 .src_wd_i (reg_wdata[0:0]),
566 .src_busy_o (wkup_cause_busy),
567 .src_qs_o (wkup_cause_qs), // for software read back
568 .dst_update_i (aon_wkup_cause_qe),
569 .dst_ds_i (aon_wkup_cause_ds),
570 .dst_qs_i (aon_wkup_cause_qs),
571 .dst_we_o (aon_wkup_cause_we),
572 .dst_re_o (),
573 .dst_regwen_o (),
574 .dst_wd_o (aon_wkup_cause_wdata)
575 );
576 1/1 assign unused_aon_wkup_cause_wdata =
Tests: T1 T2 T3
577 ^aon_wkup_cause_wdata;
578
579 // Register instances
580 // R[alert_test]: V(True)
581 logic alert_test_qe;
582 logic [0:0] alert_test_flds_we;
583 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T20 T21 T22
584 prim_subreg_ext #(
585 .DW (1)
586 ) u_alert_test (
587 .re (1'b0),
588 .we (alert_test_we),
589 .wd (alert_test_wd),
590 .d ('0),
591 .qre (),
592 .qe (alert_test_flds_we[0]),
593 .q (reg2hw.alert_test.q),
594 .ds (),
595 .qs ()
596 );
597 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T20 T21 T22
598
599
600 // R[wkup_ctrl]: V(False)
601 // F[enable]: 0:0
602 prim_subreg #(
603 .DW (1),
604 .SwAccess(prim_subreg_pkg::SwAccessRW),
605 .RESVAL (1'h0),
606 .Mubi (1'b0)
607 ) u_wkup_ctrl_enable (
608 .clk_i (clk_aon_i),
609 .rst_ni (rst_aon_ni),
610
611 // from register interface
612 .we (aon_wkup_ctrl_we),
613 .wd (aon_wkup_ctrl_wdata[0]),
614
615 // from internal hardware
616 .de (1'b0),
617 .d ('0),
618
619 // to internal hardware
620 .qe (),
621 .q (reg2hw.wkup_ctrl.enable.q),
622 .ds (),
623
624 // to register interface (read)
625 .qs (aon_wkup_ctrl_enable_qs_int)
626 );
627
628 // F[prescaler]: 12:1
629 prim_subreg #(
630 .DW (12),
631 .SwAccess(prim_subreg_pkg::SwAccessRW),
632 .RESVAL (12'h0),
633 .Mubi (1'b0)
634 ) u_wkup_ctrl_prescaler (
635 .clk_i (clk_aon_i),
636 .rst_ni (rst_aon_ni),
637
638 // from register interface
639 .we (aon_wkup_ctrl_we),
640 .wd (aon_wkup_ctrl_wdata[12:1]),
641
642 // from internal hardware
643 .de (1'b0),
644 .d ('0),
645
646 // to internal hardware
647 .qe (),
648 .q (reg2hw.wkup_ctrl.prescaler.q),
649 .ds (),
650
651 // to register interface (read)
652 .qs (aon_wkup_ctrl_prescaler_qs_int)
653 );
654
655
656 // R[wkup_thold_hi]: V(False)
657 prim_subreg #(
658 .DW (32),
659 .SwAccess(prim_subreg_pkg::SwAccessRW),
660 .RESVAL (32'h0),
661 .Mubi (1'b0)
662 ) u_wkup_thold_hi (
663 .clk_i (clk_aon_i),
664 .rst_ni (rst_aon_ni),
665
666 // from register interface
667 .we (aon_wkup_thold_hi_we),
668 .wd (aon_wkup_thold_hi_wdata[31:0]),
669
670 // from internal hardware
671 .de (1'b0),
672 .d ('0),
673
674 // to internal hardware
675 .qe (),
676 .q (reg2hw.wkup_thold_hi.q),
677 .ds (),
678
679 // to register interface (read)
680 .qs (aon_wkup_thold_hi_qs_int)
681 );
682
683
684 // R[wkup_thold_lo]: V(False)
685 prim_subreg #(
686 .DW (32),
687 .SwAccess(prim_subreg_pkg::SwAccessRW),
688 .RESVAL (32'h0),
689 .Mubi (1'b0)
690 ) u_wkup_thold_lo (
691 .clk_i (clk_aon_i),
692 .rst_ni (rst_aon_ni),
693
694 // from register interface
695 .we (aon_wkup_thold_lo_we),
696 .wd (aon_wkup_thold_lo_wdata[31:0]),
697
698 // from internal hardware
699 .de (1'b0),
700 .d ('0),
701
702 // to internal hardware
703 .qe (),
704 .q (reg2hw.wkup_thold_lo.q),
705 .ds (),
706
707 // to register interface (read)
708 .qs (aon_wkup_thold_lo_qs_int)
709 );
710
711
712 // R[wkup_count_hi]: V(False)
713 logic [0:0] wkup_count_hi_flds_we;
714 1/1 assign aon_wkup_count_hi_qe = |wkup_count_hi_flds_we;
Tests: T1 T2 T3
715 prim_subreg #(
716 .DW (32),
717 .SwAccess(prim_subreg_pkg::SwAccessRW),
718 .RESVAL (32'h0),
719 .Mubi (1'b0)
720 ) u_wkup_count_hi (
721 .clk_i (clk_aon_i),
722 .rst_ni (rst_aon_ni),
723
724 // from register interface
725 .we (aon_wkup_count_hi_we),
726 .wd (aon_wkup_count_hi_wdata[31:0]),
727
728 // from internal hardware
729 .de (hw2reg.wkup_count_hi.de),
730 .d (hw2reg.wkup_count_hi.d),
731
732 // to internal hardware
733 .qe (wkup_count_hi_flds_we[0]),
734 .q (reg2hw.wkup_count_hi.q),
735 .ds (aon_wkup_count_hi_ds_int),
736
737 // to register interface (read)
738 .qs (aon_wkup_count_hi_qs_int)
739 );
740
741
742 // R[wkup_count_lo]: V(False)
743 logic [0:0] wkup_count_lo_flds_we;
744 1/1 assign aon_wkup_count_lo_qe = |wkup_count_lo_flds_we;
Tests: T1 T2 T3
745 prim_subreg #(
746 .DW (32),
747 .SwAccess(prim_subreg_pkg::SwAccessRW),
748 .RESVAL (32'h0),
749 .Mubi (1'b0)
750 ) u_wkup_count_lo (
751 .clk_i (clk_aon_i),
752 .rst_ni (rst_aon_ni),
753
754 // from register interface
755 .we (aon_wkup_count_lo_we),
756 .wd (aon_wkup_count_lo_wdata[31:0]),
757
758 // from internal hardware
759 .de (hw2reg.wkup_count_lo.de),
760 .d (hw2reg.wkup_count_lo.d),
761
762 // to internal hardware
763 .qe (wkup_count_lo_flds_we[0]),
764 .q (reg2hw.wkup_count_lo.q),
765 .ds (aon_wkup_count_lo_ds_int),
766
767 // to register interface (read)
768 .qs (aon_wkup_count_lo_qs_int)
769 );
770
771
772 // R[wdog_regwen]: V(False)
773 prim_subreg #(
774 .DW (1),
775 .SwAccess(prim_subreg_pkg::SwAccessW0C),
776 .RESVAL (1'h1),
777 .Mubi (1'b0)
778 ) u_wdog_regwen (
779 .clk_i (clk_i),
780 .rst_ni (rst_ni),
781
782 // from register interface
783 .we (wdog_regwen_we),
784 .wd (wdog_regwen_wd),
785
786 // from internal hardware
787 .de (1'b0),
788 .d ('0),
789
790 // to internal hardware
791 .qe (),
792 .q (),
793 .ds (),
794
795 // to register interface (read)
796 .qs (wdog_regwen_qs)
797 );
798
799
800 // R[wdog_ctrl]: V(False)
801 // Create REGWEN-gated WE signal
802 logic aon_wdog_ctrl_gated_we;
803 1/1 assign aon_wdog_ctrl_gated_we = aon_wdog_ctrl_we & aon_wdog_ctrl_regwen;
Tests: T1 T2 T3
804 // F[enable]: 0:0
805 prim_subreg #(
806 .DW (1),
807 .SwAccess(prim_subreg_pkg::SwAccessRW),
808 .RESVAL (1'h0),
809 .Mubi (1'b0)
810 ) u_wdog_ctrl_enable (
811 .clk_i (clk_aon_i),
812 .rst_ni (rst_aon_ni),
813
814 // from register interface
815 .we (aon_wdog_ctrl_gated_we),
816 .wd (aon_wdog_ctrl_wdata[0]),
817
818 // from internal hardware
819 .de (1'b0),
820 .d ('0),
821
822 // to internal hardware
823 .qe (),
824 .q (reg2hw.wdog_ctrl.enable.q),
825 .ds (),
826
827 // to register interface (read)
828 .qs (aon_wdog_ctrl_enable_qs_int)
829 );
830
831 // F[pause_in_sleep]: 1:1
832 prim_subreg #(
833 .DW (1),
834 .SwAccess(prim_subreg_pkg::SwAccessRW),
835 .RESVAL (1'h0),
836 .Mubi (1'b0)
837 ) u_wdog_ctrl_pause_in_sleep (
838 .clk_i (clk_aon_i),
839 .rst_ni (rst_aon_ni),
840
841 // from register interface
842 .we (aon_wdog_ctrl_gated_we),
843 .wd (aon_wdog_ctrl_wdata[1]),
844
845 // from internal hardware
846 .de (1'b0),
847 .d ('0),
848
849 // to internal hardware
850 .qe (),
851 .q (reg2hw.wdog_ctrl.pause_in_sleep.q),
852 .ds (),
853
854 // to register interface (read)
855 .qs (aon_wdog_ctrl_pause_in_sleep_qs_int)
856 );
857
858
859 // R[wdog_bark_thold]: V(False)
860 // Create REGWEN-gated WE signal
861 logic aon_wdog_bark_thold_gated_we;
862 1/1 assign aon_wdog_bark_thold_gated_we = aon_wdog_bark_thold_we & aon_wdog_bark_thold_regwen;
Tests: T1 T2 T3
863 prim_subreg #(
864 .DW (32),
865 .SwAccess(prim_subreg_pkg::SwAccessRW),
866 .RESVAL (32'h0),
867 .Mubi (1'b0)
868 ) u_wdog_bark_thold (
869 .clk_i (clk_aon_i),
870 .rst_ni (rst_aon_ni),
871
872 // from register interface
873 .we (aon_wdog_bark_thold_gated_we),
874 .wd (aon_wdog_bark_thold_wdata[31:0]),
875
876 // from internal hardware
877 .de (1'b0),
878 .d ('0),
879
880 // to internal hardware
881 .qe (),
882 .q (reg2hw.wdog_bark_thold.q),
883 .ds (),
884
885 // to register interface (read)
886 .qs (aon_wdog_bark_thold_qs_int)
887 );
888
889
890 // R[wdog_bite_thold]: V(False)
891 // Create REGWEN-gated WE signal
892 logic aon_wdog_bite_thold_gated_we;
893 1/1 assign aon_wdog_bite_thold_gated_we = aon_wdog_bite_thold_we & aon_wdog_bite_thold_regwen;
Tests: T1 T2 T3
894 prim_subreg #(
895 .DW (32),
896 .SwAccess(prim_subreg_pkg::SwAccessRW),
897 .RESVAL (32'h0),
898 .Mubi (1'b0)
899 ) u_wdog_bite_thold (
900 .clk_i (clk_aon_i),
901 .rst_ni (rst_aon_ni),
902
903 // from register interface
904 .we (aon_wdog_bite_thold_gated_we),
905 .wd (aon_wdog_bite_thold_wdata[31:0]),
906
907 // from internal hardware
908 .de (1'b0),
909 .d ('0),
910
911 // to internal hardware
912 .qe (),
913 .q (reg2hw.wdog_bite_thold.q),
914 .ds (),
915
916 // to register interface (read)
917 .qs (aon_wdog_bite_thold_qs_int)
918 );
919
920
921 // R[wdog_count]: V(False)
922 logic [0:0] wdog_count_flds_we;
923 1/1 assign aon_wdog_count_qe = |wdog_count_flds_we;
Tests: T1 T2 T3
924 prim_subreg #(
925 .DW (32),
926 .SwAccess(prim_subreg_pkg::SwAccessRW),
927 .RESVAL (32'h0),
928 .Mubi (1'b0)
929 ) u_wdog_count (
930 .clk_i (clk_aon_i),
931 .rst_ni (rst_aon_ni),
932
933 // from register interface
934 .we (aon_wdog_count_we),
935 .wd (aon_wdog_count_wdata[31:0]),
936
937 // from internal hardware
938 .de (hw2reg.wdog_count.de),
939 .d (hw2reg.wdog_count.d),
940
941 // to internal hardware
942 .qe (wdog_count_flds_we[0]),
943 .q (reg2hw.wdog_count.q),
944 .ds (aon_wdog_count_ds_int),
945
946 // to register interface (read)
947 .qs (aon_wdog_count_qs_int)
948 );
949
950
951 // R[intr_state]: V(False)
952 // F[wkup_timer_expired]: 0:0
953 prim_subreg #(
954 .DW (1),
955 .SwAccess(prim_subreg_pkg::SwAccessW1C),
956 .RESVAL (1'h0),
957 .Mubi (1'b0)
958 ) u_intr_state_wkup_timer_expired (
959 .clk_i (clk_i),
960 .rst_ni (rst_ni),
961
962 // from register interface
963 .we (intr_state_we),
964 .wd (intr_state_wkup_timer_expired_wd),
965
966 // from internal hardware
967 .de (hw2reg.intr_state.wkup_timer_expired.de),
968 .d (hw2reg.intr_state.wkup_timer_expired.d),
969
970 // to internal hardware
971 .qe (),
972 .q (reg2hw.intr_state.wkup_timer_expired.q),
973 .ds (),
974
975 // to register interface (read)
976 .qs (intr_state_wkup_timer_expired_qs)
977 );
978
979 // F[wdog_timer_bark]: 1:1
980 prim_subreg #(
981 .DW (1),
982 .SwAccess(prim_subreg_pkg::SwAccessW1C),
983 .RESVAL (1'h0),
984 .Mubi (1'b0)
985 ) u_intr_state_wdog_timer_bark (
986 .clk_i (clk_i),
987 .rst_ni (rst_ni),
988
989 // from register interface
990 .we (intr_state_we),
991 .wd (intr_state_wdog_timer_bark_wd),
992
993 // from internal hardware
994 .de (hw2reg.intr_state.wdog_timer_bark.de),
995 .d (hw2reg.intr_state.wdog_timer_bark.d),
996
997 // to internal hardware
998 .qe (),
999 .q (reg2hw.intr_state.wdog_timer_bark.q),
1000 .ds (),
1001
1002 // to register interface (read)
1003 .qs (intr_state_wdog_timer_bark_qs)
1004 );
1005
1006
1007 // R[intr_test]: V(True)
1008 logic intr_test_qe;
1009 logic [1:0] intr_test_flds_we;
1010 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T20 T21 T22
1011 // F[wkup_timer_expired]: 0:0
1012 prim_subreg_ext #(
1013 .DW (1)
1014 ) u_intr_test_wkup_timer_expired (
1015 .re (1'b0),
1016 .we (intr_test_we),
1017 .wd (intr_test_wkup_timer_expired_wd),
1018 .d ('0),
1019 .qre (),
1020 .qe (intr_test_flds_we[0]),
1021 .q (reg2hw.intr_test.wkup_timer_expired.q),
1022 .ds (),
1023 .qs ()
1024 );
1025 1/1 assign reg2hw.intr_test.wkup_timer_expired.qe = intr_test_qe;
Tests: T20 T21 T22
1026
1027 // F[wdog_timer_bark]: 1:1
1028 prim_subreg_ext #(
1029 .DW (1)
1030 ) u_intr_test_wdog_timer_bark (
1031 .re (1'b0),
1032 .we (intr_test_we),
1033 .wd (intr_test_wdog_timer_bark_wd),
1034 .d ('0),
1035 .qre (),
1036 .qe (intr_test_flds_we[1]),
1037 .q (reg2hw.intr_test.wdog_timer_bark.q),
1038 .ds (),
1039 .qs ()
1040 );
1041 1/1 assign reg2hw.intr_test.wdog_timer_bark.qe = intr_test_qe;
Tests: T20 T21 T22
1042
1043
1044 // R[wkup_cause]: V(False)
1045 logic [0:0] wkup_cause_flds_we;
1046 1/1 assign aon_wkup_cause_qe = |wkup_cause_flds_we;
Tests: T1 T2 T3
1047 prim_subreg #(
1048 .DW (1),
1049 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1050 .RESVAL (1'h0),
1051 .Mubi (1'b0)
1052 ) u_wkup_cause (
1053 .clk_i (clk_aon_i),
1054 .rst_ni (rst_aon_ni),
1055
1056 // from register interface
1057 .we (aon_wkup_cause_we),
1058 .wd (aon_wkup_cause_wdata[0]),
1059
1060 // from internal hardware
1061 .de (hw2reg.wkup_cause.de),
1062 .d (hw2reg.wkup_cause.d),
1063
1064 // to internal hardware
1065 .qe (wkup_cause_flds_we[0]),
1066 .q (reg2hw.wkup_cause.q),
1067 .ds (aon_wkup_cause_ds_int),
1068
1069 // to register interface (read)
1070 .qs (aon_wkup_cause_qs_int)
1071 );
1072
1073
1074
1075 logic [13:0] addr_hit;
1076 always_comb begin
1077 1/1 addr_hit = '0;
Tests: T1 T2 T3
1078 1/1 addr_hit[ 0] = (reg_addr == AON_TIMER_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
1079 1/1 addr_hit[ 1] = (reg_addr == AON_TIMER_WKUP_CTRL_OFFSET);
Tests: T1 T2 T3
1080 1/1 addr_hit[ 2] = (reg_addr == AON_TIMER_WKUP_THOLD_HI_OFFSET);
Tests: T1 T2 T3
1081 1/1 addr_hit[ 3] = (reg_addr == AON_TIMER_WKUP_THOLD_LO_OFFSET);
Tests: T1 T2 T3
1082 1/1 addr_hit[ 4] = (reg_addr == AON_TIMER_WKUP_COUNT_HI_OFFSET);
Tests: T1 T2 T3
1083 1/1 addr_hit[ 5] = (reg_addr == AON_TIMER_WKUP_COUNT_LO_OFFSET);
Tests: T1 T2 T3
1084 1/1 addr_hit[ 6] = (reg_addr == AON_TIMER_WDOG_REGWEN_OFFSET);
Tests: T1 T2 T3
1085 1/1 addr_hit[ 7] = (reg_addr == AON_TIMER_WDOG_CTRL_OFFSET);
Tests: T1 T2 T3
1086 1/1 addr_hit[ 8] = (reg_addr == AON_TIMER_WDOG_BARK_THOLD_OFFSET);
Tests: T1 T2 T3
1087 1/1 addr_hit[ 9] = (reg_addr == AON_TIMER_WDOG_BITE_THOLD_OFFSET);
Tests: T1 T2 T3
1088 1/1 addr_hit[10] = (reg_addr == AON_TIMER_WDOG_COUNT_OFFSET);
Tests: T1 T2 T3
1089 1/1 addr_hit[11] = (reg_addr == AON_TIMER_INTR_STATE_OFFSET);
Tests: T1 T2 T3
1090 1/1 addr_hit[12] = (reg_addr == AON_TIMER_INTR_TEST_OFFSET);
Tests: T1 T2 T3
1091 1/1 addr_hit[13] = (reg_addr == AON_TIMER_WKUP_CAUSE_OFFSET);
Tests: T1 T2 T3
1092 end
1093
1094 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
1095
1096 // Check sub-word write is permitted
1097 always_comb begin
1098 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
1099 ((addr_hit[ 0] & (|(AON_TIMER_PERMIT[ 0] & ~reg_be))) |
1100 (addr_hit[ 1] & (|(AON_TIMER_PERMIT[ 1] & ~reg_be))) |
1101 (addr_hit[ 2] & (|(AON_TIMER_PERMIT[ 2] & ~reg_be))) |
1102 (addr_hit[ 3] & (|(AON_TIMER_PERMIT[ 3] & ~reg_be))) |
1103 (addr_hit[ 4] & (|(AON_TIMER_PERMIT[ 4] & ~reg_be))) |
1104 (addr_hit[ 5] & (|(AON_TIMER_PERMIT[ 5] & ~reg_be))) |
1105 (addr_hit[ 6] & (|(AON_TIMER_PERMIT[ 6] & ~reg_be))) |
1106 (addr_hit[ 7] & (|(AON_TIMER_PERMIT[ 7] & ~reg_be))) |
1107 (addr_hit[ 8] & (|(AON_TIMER_PERMIT[ 8] & ~reg_be))) |
1108 (addr_hit[ 9] & (|(AON_TIMER_PERMIT[ 9] & ~reg_be))) |
1109 (addr_hit[10] & (|(AON_TIMER_PERMIT[10] & ~reg_be))) |
1110 (addr_hit[11] & (|(AON_TIMER_PERMIT[11] & ~reg_be))) |
1111 (addr_hit[12] & (|(AON_TIMER_PERMIT[12] & ~reg_be))) |
1112 (addr_hit[13] & (|(AON_TIMER_PERMIT[13] & ~reg_be)))));
1113 end
1114
1115 // Generate write-enables
1116 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
1117
1118 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
1119 1/1 assign wkup_ctrl_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
1120
1121
1122 1/1 assign wkup_thold_hi_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
1123
1124 1/1 assign wkup_thold_lo_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
1125
1126 1/1 assign wkup_count_hi_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
1127
1128 1/1 assign wkup_count_lo_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
1129
1130 1/1 assign wdog_regwen_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
1131
1132 1/1 assign wdog_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
1133 1/1 assign wdog_ctrl_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
1134
1135
1136 1/1 assign wdog_bark_thold_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
1137
1138 1/1 assign wdog_bite_thold_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
1139
1140 1/1 assign wdog_count_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
1141
1142 1/1 assign intr_state_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
1143
1144 1/1 assign intr_state_wkup_timer_expired_wd = reg_wdata[0];
Tests: T1 T2 T3
1145
1146 1/1 assign intr_state_wdog_timer_bark_wd = reg_wdata[1];
Tests: T1 T2 T3
1147 1/1 assign intr_test_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
1148
1149 1/1 assign intr_test_wkup_timer_expired_wd = reg_wdata[0];
Tests: T1 T2 T3
1150
1151 1/1 assign intr_test_wdog_timer_bark_wd = reg_wdata[1];
Tests: T1 T2 T3
1152 1/1 assign wkup_cause_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
1153
1154
1155 // Assign write-enables to checker logic vector.
1156 always_comb begin
1157 1/1 reg_we_check = '0;
Tests: T1 T2 T3
1158 1/1 reg_we_check[0] = alert_test_we;
Tests: T1 T2 T3
1159 1/1 reg_we_check[1] = wkup_ctrl_we;
Tests: T1 T2 T3
1160 1/1 reg_we_check[2] = wkup_thold_hi_we;
Tests: T1 T2 T3
1161 1/1 reg_we_check[3] = wkup_thold_lo_we;
Tests: T1 T2 T3
1162 1/1 reg_we_check[4] = wkup_count_hi_we;
Tests: T1 T2 T3
1163 1/1 reg_we_check[5] = wkup_count_lo_we;
Tests: T1 T2 T3
1164 1/1 reg_we_check[6] = wdog_regwen_we;
Tests: T1 T2 T3
1165 1/1 reg_we_check[7] = wdog_ctrl_we;
Tests: T1 T2 T3
1166 1/1 reg_we_check[8] = wdog_bark_thold_we;
Tests: T1 T2 T3
1167 1/1 reg_we_check[9] = wdog_bite_thold_we;
Tests: T1 T2 T3
1168 1/1 reg_we_check[10] = wdog_count_we;
Tests: T1 T2 T3
1169 1/1 reg_we_check[11] = intr_state_we;
Tests: T1 T2 T3
1170 1/1 reg_we_check[12] = intr_test_we;
Tests: T1 T2 T3
1171 1/1 reg_we_check[13] = wkup_cause_we;
Tests: T1 T2 T3
1172 end
1173
1174 // Read data return
1175 always_comb begin
1176 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
1177 1/1 unique case (1'b1)
Tests: T1 T2 T3
1178 addr_hit[0]: begin
1179 1/1 reg_rdata_next[0] = '0;
Tests: T2 T3 T4
1180 end
1181
1182 addr_hit[1]: begin
1183 1/1 reg_rdata_next = DW'(wkup_ctrl_qs);
Tests: T1 T2 T3
1184 end
1185 addr_hit[2]: begin
1186 1/1 reg_rdata_next = DW'(wkup_thold_hi_qs);
Tests: T1 T2 T3
1187 end
1188 addr_hit[3]: begin
1189 1/1 reg_rdata_next = DW'(wkup_thold_lo_qs);
Tests: T1 T2 T3
1190 end
1191 addr_hit[4]: begin
1192 1/1 reg_rdata_next = DW'(wkup_count_hi_qs);
Tests: T1 T2 T3
1193 end
1194 addr_hit[5]: begin
1195 1/1 reg_rdata_next = DW'(wkup_count_lo_qs);
Tests: T1 T2 T3
1196 end
1197 addr_hit[6]: begin
1198 1/1 reg_rdata_next[0] = wdog_regwen_qs;
Tests: T1 T2 T3
1199 end
1200
1201 addr_hit[7]: begin
1202 1/1 reg_rdata_next = DW'(wdog_ctrl_qs);
Tests: T1 T2 T3
1203 end
1204 addr_hit[8]: begin
1205 1/1 reg_rdata_next = DW'(wdog_bark_thold_qs);
Tests: T1 T2 T3
1206 end
1207 addr_hit[9]: begin
1208 1/1 reg_rdata_next = DW'(wdog_bite_thold_qs);
Tests: T1 T2 T3
1209 end
1210 addr_hit[10]: begin
1211 1/1 reg_rdata_next = DW'(wdog_count_qs);
Tests: T1 T2 T3
1212 end
1213 addr_hit[11]: begin
1214 1/1 reg_rdata_next[0] = intr_state_wkup_timer_expired_qs;
Tests: T1 T2 T3
1215 1/1 reg_rdata_next[1] = intr_state_wdog_timer_bark_qs;
Tests: T1 T2 T3
1216 end
1217
1218 addr_hit[12]: begin
1219 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1220 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
1221 end
1222
1223 addr_hit[13]: begin
1224 1/1 reg_rdata_next = DW'(wkup_cause_qs);
Tests: T1 T2 T3
1225 end
1226 default: begin
1227 reg_rdata_next = '1;
1228 end
1229 endcase
1230 end
1231
1232 // shadow busy
1233 logic shadow_busy;
1234 assign shadow_busy = 1'b0;
1235
1236 // register busy
1237 logic reg_busy_sel;
1238 1/1 assign reg_busy = reg_busy_sel | shadow_busy;
Tests: T1 T2 T3
1239 always_comb begin
1240 1/1 reg_busy_sel = '0;
Tests: T1 T2 T3
1241 1/1 unique case (1'b1)
Tests: T1 T2 T3
1242 addr_hit[1]: begin
1243 1/1 reg_busy_sel = wkup_ctrl_busy;
Tests: T1 T2 T3
1244 end
1245 addr_hit[2]: begin
1246 1/1 reg_busy_sel = wkup_thold_hi_busy;
Tests: T1 T2 T3
1247 end
1248 addr_hit[3]: begin
1249 1/1 reg_busy_sel = wkup_thold_lo_busy;
Tests: T1 T2 T3
1250 end
1251 addr_hit[4]: begin
1252 1/1 reg_busy_sel = wkup_count_hi_busy;
Tests: T1 T2 T3
1253 end
1254 addr_hit[5]: begin
1255 1/1 reg_busy_sel = wkup_count_lo_busy;
Tests: T1 T2 T3
1256 end
1257 addr_hit[7]: begin
1258 1/1 reg_busy_sel = wdog_ctrl_busy;
Tests: T1 T2 T3
1259 end
1260 addr_hit[8]: begin
1261 1/1 reg_busy_sel = wdog_bark_thold_busy;
Tests: T1 T2 T3
1262 end
1263 addr_hit[9]: begin
1264 1/1 reg_busy_sel = wdog_bite_thold_busy;
Tests: T1 T2 T3
1265 end
1266 addr_hit[10]: begin
1267 1/1 reg_busy_sel = wdog_count_busy;
Tests: T1 T2 T3
1268 end
1269 addr_hit[13]: begin
1270 1/1 reg_busy_sel = wkup_cause_busy;
Tests: T1 T2 T3
1271 end
1272 default: begin
1273 reg_busy_sel = '0;
1274 end
1275 endcase
1276 end
1277
1278
1279 // Unused signal tieoff
1280
1281 // wdata / byte enable are not always fully used
1282 // add a blanket unused statement to handle lint waivers
1283 logic unused_wdata;
1284 logic unused_be;
1285 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
1286 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3
Cond Coverage for Module :
aon_timer_reg_top
| Total | Covered | Percent |
|---|
| Conditions | 174 | 171 | 98.28 |
| Logical | 174 | 171 | 98.28 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T11,T25,T26 |
| 1 | 0 | Covered | T36,T39,T40 |
LINE 79
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T11,T25,T26 |
| 0 | 1 | 0 | Covered | T36,T39,T40 |
| 1 | 0 | 0 | Covered | T11,T25,T26 |
LINE 121
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T36,T39,T40 |
| 0 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 0 | 0 | Covered | T20,T21,T22 |
LINE 803
EXPRESSION (aon_wdog_ctrl_we & aon_wdog_ctrl_regwen)
--------1------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T3,T4,T6 |
| 1 | 1 | Covered | T1,T2,T5 |
LINE 862
EXPRESSION (aon_wdog_bark_thold_we & aon_wdog_bark_thold_regwen)
-----------1---------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T20,T21,T27 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 893
EXPRESSION (aon_wdog_bite_thold_we & aon_wdog_bite_thold_regwen)
-----------1---------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T20,T21,T27 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1078
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_ALERT_TEST_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T16 |
LINE 1079
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CTRL_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1080
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_THOLD_HI_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1081
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_THOLD_LO_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1082
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_COUNT_HI_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1083
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_COUNT_LO_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1084
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_REGWEN_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1085
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_CTRL_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1086
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BARK_THOLD_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1087
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BITE_THOLD_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1088
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_COUNT_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1089
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_STATE_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1090
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_TEST_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T24 |
LINE 1091
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CAUSE_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1094
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1094
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 1098
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 1098
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))))
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Covered | T1,T16,T18 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T1,T3,T17 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T1,T16,T19 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T1,T24,T16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T24 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T24,T16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T16,T17,T19 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T24,T17 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T24 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T24,T16 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T24 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T24,T16,T17 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T24,T16,T18 |
LINE 1098
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T17,T20 |
| 1 | 1 | Covered | T24,T16,T18 |
LINE 1098
SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T24,T16,T17 |
LINE 1098
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T24 |
LINE 1098
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T24,T16 |
LINE 1098
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T24 |
LINE 1098
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T24,T17 |
LINE 1098
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T16,T17,T19 |
LINE 1098
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T24,T16 |
LINE 1098
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T24 |
LINE 1098
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T24,T16 |
LINE 1098
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T16,T19 |
LINE 1098
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T24 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1098
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T24,T16 |
| 1 | 1 | Covered | T1,T3,T17 |
LINE 1098
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T16,T18 |
LINE 1116
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T24,T16 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T36,T41,T42 |
LINE 1119
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1122
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1124
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1126
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1128
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1130
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1133
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1136
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1138
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1140
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1142
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1147
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T3,T24 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T20,T27,T43 |
LINE 1152
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1238
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
Branch Coverage for Module :
aon_timer_reg_top
| Line No. | Total | Covered | Percent |
| Branches |
|
31 |
31 |
100.00 |
| TERNARY |
1094 |
2 |
2 |
100.00 |
| IF |
70 |
3 |
3 |
100.00 |
| CASE |
1177 |
15 |
15 |
100.00 |
| CASE |
1241 |
11 |
11 |
100.00 |
1094 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
70 if (!rst_ni) begin
-1-
71 err_q <= '0;
==>
72 end else if (intg_err || reg_we_err) begin
-2-
73 err_q <= 1'b1;
==>
74 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T11,T25,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
1177 unique case (1'b1)
-1-
1178 addr_hit[0]: begin
1179 reg_rdata_next[0] = '0;
==>
1180 end
1181
1182 addr_hit[1]: begin
1183 reg_rdata_next = DW'(wkup_ctrl_qs);
==>
1184 end
1185 addr_hit[2]: begin
1186 reg_rdata_next = DW'(wkup_thold_hi_qs);
==>
1187 end
1188 addr_hit[3]: begin
1189 reg_rdata_next = DW'(wkup_thold_lo_qs);
==>
1190 end
1191 addr_hit[4]: begin
1192 reg_rdata_next = DW'(wkup_count_hi_qs);
==>
1193 end
1194 addr_hit[5]: begin
1195 reg_rdata_next = DW'(wkup_count_lo_qs);
==>
1196 end
1197 addr_hit[6]: begin
1198 reg_rdata_next[0] = wdog_regwen_qs;
==>
1199 end
1200
1201 addr_hit[7]: begin
1202 reg_rdata_next = DW'(wdog_ctrl_qs);
==>
1203 end
1204 addr_hit[8]: begin
1205 reg_rdata_next = DW'(wdog_bark_thold_qs);
==>
1206 end
1207 addr_hit[9]: begin
1208 reg_rdata_next = DW'(wdog_bite_thold_qs);
==>
1209 end
1210 addr_hit[10]: begin
1211 reg_rdata_next = DW'(wdog_count_qs);
==>
1212 end
1213 addr_hit[11]: begin
1214 reg_rdata_next[0] = intr_state_wkup_timer_expired_qs;
==>
1215 reg_rdata_next[1] = intr_state_wdog_timer_bark_qs;
1216 end
1217
1218 addr_hit[12]: begin
1219 reg_rdata_next[0] = '0;
==>
1220 reg_rdata_next[1] = '0;
1221 end
1222
1223 addr_hit[13]: begin
1224 reg_rdata_next = DW'(wkup_cause_qs);
==>
1225 end
1226 default: begin
1227 reg_rdata_next = '1;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[0] |
Covered |
T2,T3,T4 |
| addr_hit[1] |
Covered |
T1,T2,T3 |
| addr_hit[2] |
Covered |
T1,T2,T3 |
| addr_hit[3] |
Covered |
T1,T2,T3 |
| addr_hit[4] |
Covered |
T1,T2,T3 |
| addr_hit[5] |
Covered |
T1,T2,T3 |
| addr_hit[6] |
Covered |
T1,T2,T3 |
| addr_hit[7] |
Covered |
T1,T2,T3 |
| addr_hit[8] |
Covered |
T1,T2,T3 |
| addr_hit[9] |
Covered |
T1,T2,T3 |
| addr_hit[10] |
Covered |
T1,T2,T3 |
| addr_hit[11] |
Covered |
T1,T2,T3 |
| addr_hit[12] |
Covered |
T1,T2,T3 |
| addr_hit[13] |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
1241 unique case (1'b1)
-1-
1242 addr_hit[1]: begin
1243 reg_busy_sel = wkup_ctrl_busy;
==>
1244 end
1245 addr_hit[2]: begin
1246 reg_busy_sel = wkup_thold_hi_busy;
==>
1247 end
1248 addr_hit[3]: begin
1249 reg_busy_sel = wkup_thold_lo_busy;
==>
1250 end
1251 addr_hit[4]: begin
1252 reg_busy_sel = wkup_count_hi_busy;
==>
1253 end
1254 addr_hit[5]: begin
1255 reg_busy_sel = wkup_count_lo_busy;
==>
1256 end
1257 addr_hit[7]: begin
1258 reg_busy_sel = wdog_ctrl_busy;
==>
1259 end
1260 addr_hit[8]: begin
1261 reg_busy_sel = wdog_bark_thold_busy;
==>
1262 end
1263 addr_hit[9]: begin
1264 reg_busy_sel = wdog_bite_thold_busy;
==>
1265 end
1266 addr_hit[10]: begin
1267 reg_busy_sel = wdog_count_busy;
==>
1268 end
1269 addr_hit[13]: begin
1270 reg_busy_sel = wkup_cause_busy;
==>
1271 end
1272 default: begin
1273 reg_busy_sel = '0;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[1] |
Covered |
T1,T2,T3 |
| addr_hit[2] |
Covered |
T1,T2,T3 |
| addr_hit[3] |
Covered |
T1,T2,T3 |
| addr_hit[4] |
Covered |
T1,T2,T3 |
| addr_hit[5] |
Covered |
T1,T2,T3 |
| addr_hit[7] |
Covered |
T1,T2,T3 |
| addr_hit[8] |
Covered |
T1,T2,T3 |
| addr_hit[9] |
Covered |
T1,T2,T3 |
| addr_hit[10] |
Covered |
T1,T2,T3 |
| addr_hit[13] |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
aon_timer_reg_top
Assertion Details
en2addrHit
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
517111313 |
75702 |
0 |
0 |
| T1 |
2792 |
19 |
0 |
0 |
| T2 |
9291 |
22 |
0 |
0 |
| T3 |
10866 |
18 |
0 |
0 |
| T4 |
6752 |
22 |
0 |
0 |
| T5 |
11274 |
19 |
0 |
0 |
| T6 |
39008 |
18 |
0 |
0 |
| T7 |
53258 |
22 |
0 |
0 |
| T8 |
3101 |
22 |
0 |
0 |
| T9 |
39727 |
18 |
0 |
0 |
| T10 |
0 |
19 |
0 |
0 |
| T11 |
56557 |
0 |
0 |
0 |
reAfterRv
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
517111313 |
75702 |
0 |
0 |
| T1 |
2792 |
19 |
0 |
0 |
| T2 |
9291 |
22 |
0 |
0 |
| T3 |
10866 |
18 |
0 |
0 |
| T4 |
6752 |
22 |
0 |
0 |
| T5 |
11274 |
19 |
0 |
0 |
| T6 |
39008 |
18 |
0 |
0 |
| T7 |
53258 |
22 |
0 |
0 |
| T8 |
3101 |
22 |
0 |
0 |
| T9 |
39727 |
18 |
0 |
0 |
| T10 |
0 |
19 |
0 |
0 |
| T11 |
56557 |
0 |
0 |
0 |
rePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
517111313 |
20860 |
0 |
0 |
| T1 |
2792 |
1 |
0 |
0 |
| T2 |
9291 |
1 |
0 |
0 |
| T3 |
10866 |
1 |
0 |
0 |
| T4 |
6752 |
1 |
0 |
0 |
| T5 |
11274 |
1 |
0 |
0 |
| T6 |
39008 |
1 |
0 |
0 |
| T7 |
53258 |
1 |
0 |
0 |
| T8 |
3101 |
1 |
0 |
0 |
| T9 |
39727 |
1 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
56557 |
0 |
0 |
0 |
wePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
517111313 |
54842 |
0 |
0 |
| T1 |
2792 |
18 |
0 |
0 |
| T2 |
9291 |
21 |
0 |
0 |
| T3 |
10866 |
17 |
0 |
0 |
| T4 |
6752 |
21 |
0 |
0 |
| T5 |
11274 |
18 |
0 |
0 |
| T6 |
39008 |
17 |
0 |
0 |
| T7 |
53258 |
21 |
0 |
0 |
| T8 |
3101 |
21 |
0 |
0 |
| T9 |
39727 |
17 |
0 |
0 |
| T10 |
0 |
18 |
0 |
0 |
| T11 |
56557 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 146 | 146 | 100.00 |
| ALWAYS | 70 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 209 | 1 | 1 | 100.00 |
| ALWAYS | 219 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
| ALWAYS | 257 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| ALWAYS | 298 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 328 | 1 | 1 | 100.00 |
| ALWAYS | 341 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 371 | 1 | 1 | 100.00 |
| ALWAYS | 383 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
| ALWAYS | 423 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
| ALWAYS | 462 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 490 | 1 | 1 | 100.00 |
| ALWAYS | 503 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 533 | 1 | 1 | 100.00 |
| ALWAYS | 546 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 576 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 583 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 597 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 714 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 744 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 803 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 862 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 893 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 923 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1010 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1025 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1041 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1046 | 1 | 1 | 100.00 |
| ALWAYS | 1077 | 15 | 15 | 100.00 |
| CONT_ASSIGN | 1094 | 1 | 1 | 100.00 |
| ALWAYS | 1098 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1124 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1152 | 1 | 1 | 100.00 |
| ALWAYS | 1157 | 15 | 15 | 100.00 |
| ALWAYS | 1176 | 18 | 18 | 100.00 |
| CONT_ASSIGN | 1238 | 1 | 1 | 100.00 |
| ALWAYS | 1240 | 12 | 12 | 100.00 |
| CONT_ASSIGN | 1285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1286 | 1 | 1 | 100.00 |
69 always_ff @(posedge clk_i or negedge rst_ni) begin
70 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
71 1/1 err_q <= '0;
Tests: T1 T2 T3
72 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
73 1/1 err_q <= 1'b1;
Tests: T11 T25 T26
74 end
MISSING_ELSE
75 end
76
77 // integrity error output is permanent and should be used for alert generation
78 // register errors are transactional
79 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
80
81 // outgoing integrity generation
82 tlul_pkg::tl_d2h_t tl_o_pre;
83 tlul_rsp_intg_gen #(
84 .EnableRspIntgGen(1),
85 .EnableDataIntgGen(1)
86 ) u_rsp_intg_gen (
87 .tl_i(tl_o_pre),
88 .tl_o(tl_o)
89 );
90
91 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
92 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
93
94 tlul_adapter_reg #(
95 .RegAw(AW),
96 .RegDw(DW),
97 .EnableDataIntgGen(0)
98 ) u_reg_if (
99 .clk_i (clk_i),
100 .rst_ni (rst_ni),
101
102 .tl_i (tl_reg_h2d),
103 .tl_o (tl_reg_d2h),
104
105 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
106 .intg_error_o(),
107
108 .we_o (reg_we),
109 .re_o (reg_re),
110 .addr_o (reg_addr),
111 .wdata_o (reg_wdata),
112 .be_o (reg_be),
113 .busy_i (reg_busy),
114 .rdata_i (reg_rdata),
115 .error_i (reg_error)
116 );
117
118 // cdc oversampling signals
119
120 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
121 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T2 T4 T5
122
123 // Define SW related signals
124 // Format: <reg>_<field>_{wd|we|qs}
125 // or <reg>_{wd|we|qs} if field == 1 or 0
126 logic alert_test_we;
127 logic alert_test_wd;
128 logic wkup_ctrl_we;
129 logic [12:0] wkup_ctrl_qs;
130 logic wkup_ctrl_busy;
131 logic wkup_thold_hi_we;
132 logic [31:0] wkup_thold_hi_qs;
133 logic wkup_thold_hi_busy;
134 logic wkup_thold_lo_we;
135 logic [31:0] wkup_thold_lo_qs;
136 logic wkup_thold_lo_busy;
137 logic wkup_count_hi_we;
138 logic [31:0] wkup_count_hi_qs;
139 logic wkup_count_hi_busy;
140 logic wkup_count_lo_we;
141 logic [31:0] wkup_count_lo_qs;
142 logic wkup_count_lo_busy;
143 logic wdog_regwen_we;
144 logic wdog_regwen_qs;
145 logic wdog_regwen_wd;
146 logic wdog_ctrl_we;
147 logic [1:0] wdog_ctrl_qs;
148 logic wdog_ctrl_busy;
149 logic wdog_bark_thold_we;
150 logic [31:0] wdog_bark_thold_qs;
151 logic wdog_bark_thold_busy;
152 logic wdog_bite_thold_we;
153 logic [31:0] wdog_bite_thold_qs;
154 logic wdog_bite_thold_busy;
155 logic wdog_count_we;
156 logic [31:0] wdog_count_qs;
157 logic wdog_count_busy;
158 logic intr_state_we;
159 logic intr_state_wkup_timer_expired_qs;
160 logic intr_state_wkup_timer_expired_wd;
161 logic intr_state_wdog_timer_bark_qs;
162 logic intr_state_wdog_timer_bark_wd;
163 logic intr_test_we;
164 logic intr_test_wkup_timer_expired_wd;
165 logic intr_test_wdog_timer_bark_wd;
166 logic wkup_cause_we;
167 logic [0:0] wkup_cause_qs;
168 logic wkup_cause_busy;
169 // Define register CDC handling.
170 // CDC handling is done on a per-reg instead of per-field boundary.
171
172 logic aon_wkup_ctrl_enable_qs_int;
173 logic [11:0] aon_wkup_ctrl_prescaler_qs_int;
174 logic [12:0] aon_wkup_ctrl_qs;
175 logic [12:0] aon_wkup_ctrl_wdata;
176 logic aon_wkup_ctrl_we;
177 logic unused_aon_wkup_ctrl_wdata;
178
179 always_comb begin
180 1/1 aon_wkup_ctrl_qs = 13'h0;
Tests: T1 T2 T3
181 1/1 aon_wkup_ctrl_qs[0] = aon_wkup_ctrl_enable_qs_int;
Tests: T1 T2 T3
182 1/1 aon_wkup_ctrl_qs[12:1] = aon_wkup_ctrl_prescaler_qs_int;
Tests: T1 T2 T3
183 end
184
185 prim_reg_cdc #(
186 .DataWidth(13),
187 .ResetVal(13'h0),
188 .BitMask(13'h1fff),
189 .DstWrReq(0)
190 ) u_wkup_ctrl_cdc (
191 .clk_src_i (clk_i),
192 .rst_src_ni (rst_ni),
193 .clk_dst_i (clk_aon_i),
194 .rst_dst_ni (rst_aon_ni),
195 .src_regwen_i ('0),
196 .src_we_i (wkup_ctrl_we),
197 .src_re_i ('0),
198 .src_wd_i (reg_wdata[12:0]),
199 .src_busy_o (wkup_ctrl_busy),
200 .src_qs_o (wkup_ctrl_qs), // for software read back
201 .dst_update_i ('0),
202 .dst_ds_i ('0),
203 .dst_qs_i (aon_wkup_ctrl_qs),
204 .dst_we_o (aon_wkup_ctrl_we),
205 .dst_re_o (),
206 .dst_regwen_o (),
207 .dst_wd_o (aon_wkup_ctrl_wdata)
208 );
209 1/1 assign unused_aon_wkup_ctrl_wdata =
Tests: T1 T2 T3
210 ^aon_wkup_ctrl_wdata;
211
212 logic [31:0] aon_wkup_thold_hi_qs_int;
213 logic [31:0] aon_wkup_thold_hi_qs;
214 logic [31:0] aon_wkup_thold_hi_wdata;
215 logic aon_wkup_thold_hi_we;
216 logic unused_aon_wkup_thold_hi_wdata;
217
218 always_comb begin
219 1/1 aon_wkup_thold_hi_qs = 32'h0;
Tests: T2 T4 T7
220 1/1 aon_wkup_thold_hi_qs = aon_wkup_thold_hi_qs_int;
Tests: T2 T4 T7
221 end
222
223 prim_reg_cdc #(
224 .DataWidth(32),
225 .ResetVal(32'h0),
226 .BitMask(32'hffffffff),
227 .DstWrReq(0)
228 ) u_wkup_thold_hi_cdc (
229 .clk_src_i (clk_i),
230 .rst_src_ni (rst_ni),
231 .clk_dst_i (clk_aon_i),
232 .rst_dst_ni (rst_aon_ni),
233 .src_regwen_i ('0),
234 .src_we_i (wkup_thold_hi_we),
235 .src_re_i ('0),
236 .src_wd_i (reg_wdata[31:0]),
237 .src_busy_o (wkup_thold_hi_busy),
238 .src_qs_o (wkup_thold_hi_qs), // for software read back
239 .dst_update_i ('0),
240 .dst_ds_i ('0),
241 .dst_qs_i (aon_wkup_thold_hi_qs),
242 .dst_we_o (aon_wkup_thold_hi_we),
243 .dst_re_o (),
244 .dst_regwen_o (),
245 .dst_wd_o (aon_wkup_thold_hi_wdata)
246 );
247 1/1 assign unused_aon_wkup_thold_hi_wdata =
Tests: T1 T2 T3
248 ^aon_wkup_thold_hi_wdata;
249
250 logic [31:0] aon_wkup_thold_lo_qs_int;
251 logic [31:0] aon_wkup_thold_lo_qs;
252 logic [31:0] aon_wkup_thold_lo_wdata;
253 logic aon_wkup_thold_lo_we;
254 logic unused_aon_wkup_thold_lo_wdata;
255
256 always_comb begin
257 1/1 aon_wkup_thold_lo_qs = 32'h0;
Tests: T1 T2 T3
258 1/1 aon_wkup_thold_lo_qs = aon_wkup_thold_lo_qs_int;
Tests: T1 T2 T3
259 end
260
261 prim_reg_cdc #(
262 .DataWidth(32),
263 .ResetVal(32'h0),
264 .BitMask(32'hffffffff),
265 .DstWrReq(0)
266 ) u_wkup_thold_lo_cdc (
267 .clk_src_i (clk_i),
268 .rst_src_ni (rst_ni),
269 .clk_dst_i (clk_aon_i),
270 .rst_dst_ni (rst_aon_ni),
271 .src_regwen_i ('0),
272 .src_we_i (wkup_thold_lo_we),
273 .src_re_i ('0),
274 .src_wd_i (reg_wdata[31:0]),
275 .src_busy_o (wkup_thold_lo_busy),
276 .src_qs_o (wkup_thold_lo_qs), // for software read back
277 .dst_update_i ('0),
278 .dst_ds_i ('0),
279 .dst_qs_i (aon_wkup_thold_lo_qs),
280 .dst_we_o (aon_wkup_thold_lo_we),
281 .dst_re_o (),
282 .dst_regwen_o (),
283 .dst_wd_o (aon_wkup_thold_lo_wdata)
284 );
285 1/1 assign unused_aon_wkup_thold_lo_wdata =
Tests: T1 T2 T3
286 ^aon_wkup_thold_lo_wdata;
287
288 logic [31:0] aon_wkup_count_hi_ds_int;
289 logic [31:0] aon_wkup_count_hi_qs_int;
290 logic [31:0] aon_wkup_count_hi_ds;
291 logic aon_wkup_count_hi_qe;
292 logic [31:0] aon_wkup_count_hi_qs;
293 logic [31:0] aon_wkup_count_hi_wdata;
294 logic aon_wkup_count_hi_we;
295 logic unused_aon_wkup_count_hi_wdata;
296
297 always_comb begin
298 1/1 aon_wkup_count_hi_qs = 32'h0;
Tests: T2 T4 T7
299 1/1 aon_wkup_count_hi_ds = 32'h0;
Tests: T2 T4 T7
300 1/1 aon_wkup_count_hi_ds = aon_wkup_count_hi_ds_int;
Tests: T2 T4 T7
301 1/1 aon_wkup_count_hi_qs = aon_wkup_count_hi_qs_int;
Tests: T2 T4 T7
302 end
303
304 prim_reg_cdc #(
305 .DataWidth(32),
306 .ResetVal(32'h0),
307 .BitMask(32'hffffffff),
308 .DstWrReq(1)
309 ) u_wkup_count_hi_cdc (
310 .clk_src_i (clk_i),
311 .rst_src_ni (rst_ni),
312 .clk_dst_i (clk_aon_i),
313 .rst_dst_ni (rst_aon_ni),
314 .src_regwen_i ('0),
315 .src_we_i (wkup_count_hi_we),
316 .src_re_i ('0),
317 .src_wd_i (reg_wdata[31:0]),
318 .src_busy_o (wkup_count_hi_busy),
319 .src_qs_o (wkup_count_hi_qs), // for software read back
320 .dst_update_i (aon_wkup_count_hi_qe),
321 .dst_ds_i (aon_wkup_count_hi_ds),
322 .dst_qs_i (aon_wkup_count_hi_qs),
323 .dst_we_o (aon_wkup_count_hi_we),
324 .dst_re_o (),
325 .dst_regwen_o (),
326 .dst_wd_o (aon_wkup_count_hi_wdata)
327 );
328 1/1 assign unused_aon_wkup_count_hi_wdata =
Tests: T1 T2 T3
329 ^aon_wkup_count_hi_wdata;
330
331 logic [31:0] aon_wkup_count_lo_ds_int;
332 logic [31:0] aon_wkup_count_lo_qs_int;
333 logic [31:0] aon_wkup_count_lo_ds;
334 logic aon_wkup_count_lo_qe;
335 logic [31:0] aon_wkup_count_lo_qs;
336 logic [31:0] aon_wkup_count_lo_wdata;
337 logic aon_wkup_count_lo_we;
338 logic unused_aon_wkup_count_lo_wdata;
339
340 always_comb begin
341 1/1 aon_wkup_count_lo_qs = 32'h0;
Tests: T1 T2 T3
342 1/1 aon_wkup_count_lo_ds = 32'h0;
Tests: T1 T2 T3
343 1/1 aon_wkup_count_lo_ds = aon_wkup_count_lo_ds_int;
Tests: T1 T2 T3
344 1/1 aon_wkup_count_lo_qs = aon_wkup_count_lo_qs_int;
Tests: T1 T2 T3
345 end
346
347 prim_reg_cdc #(
348 .DataWidth(32),
349 .ResetVal(32'h0),
350 .BitMask(32'hffffffff),
351 .DstWrReq(1)
352 ) u_wkup_count_lo_cdc (
353 .clk_src_i (clk_i),
354 .rst_src_ni (rst_ni),
355 .clk_dst_i (clk_aon_i),
356 .rst_dst_ni (rst_aon_ni),
357 .src_regwen_i ('0),
358 .src_we_i (wkup_count_lo_we),
359 .src_re_i ('0),
360 .src_wd_i (reg_wdata[31:0]),
361 .src_busy_o (wkup_count_lo_busy),
362 .src_qs_o (wkup_count_lo_qs), // for software read back
363 .dst_update_i (aon_wkup_count_lo_qe),
364 .dst_ds_i (aon_wkup_count_lo_ds),
365 .dst_qs_i (aon_wkup_count_lo_qs),
366 .dst_we_o (aon_wkup_count_lo_we),
367 .dst_re_o (),
368 .dst_regwen_o (),
369 .dst_wd_o (aon_wkup_count_lo_wdata)
370 );
371 1/1 assign unused_aon_wkup_count_lo_wdata =
Tests: T1 T2 T3
372 ^aon_wkup_count_lo_wdata;
373
374 logic aon_wdog_ctrl_enable_qs_int;
375 logic aon_wdog_ctrl_pause_in_sleep_qs_int;
376 logic [1:0] aon_wdog_ctrl_qs;
377 logic [1:0] aon_wdog_ctrl_wdata;
378 logic aon_wdog_ctrl_we;
379 logic unused_aon_wdog_ctrl_wdata;
380 logic aon_wdog_ctrl_regwen;
381
382 always_comb begin
383 1/1 aon_wdog_ctrl_qs = 2'h0;
Tests: T1 T2 T5
384 1/1 aon_wdog_ctrl_qs[0] = aon_wdog_ctrl_enable_qs_int;
Tests: T1 T2 T5
385 1/1 aon_wdog_ctrl_qs[1] = aon_wdog_ctrl_pause_in_sleep_qs_int;
Tests: T1 T2 T5
386 end
387
388 prim_reg_cdc #(
389 .DataWidth(2),
390 .ResetVal(2'h0),
391 .BitMask(2'h3),
392 .DstWrReq(0)
393 ) u_wdog_ctrl_cdc (
394 .clk_src_i (clk_i),
395 .rst_src_ni (rst_ni),
396 .clk_dst_i (clk_aon_i),
397 .rst_dst_ni (rst_aon_ni),
398 .src_regwen_i (wdog_regwen_qs),
399 .src_we_i (wdog_ctrl_we),
400 .src_re_i ('0),
401 .src_wd_i (reg_wdata[1:0]),
402 .src_busy_o (wdog_ctrl_busy),
403 .src_qs_o (wdog_ctrl_qs), // for software read back
404 .dst_update_i ('0),
405 .dst_ds_i ('0),
406 .dst_qs_i (aon_wdog_ctrl_qs),
407 .dst_we_o (aon_wdog_ctrl_we),
408 .dst_re_o (),
409 .dst_regwen_o (aon_wdog_ctrl_regwen),
410 .dst_wd_o (aon_wdog_ctrl_wdata)
411 );
412 1/1 assign unused_aon_wdog_ctrl_wdata =
Tests: T1 T2 T3
413 ^aon_wdog_ctrl_wdata;
414
415 logic [31:0] aon_wdog_bark_thold_qs_int;
416 logic [31:0] aon_wdog_bark_thold_qs;
417 logic [31:0] aon_wdog_bark_thold_wdata;
418 logic aon_wdog_bark_thold_we;
419 logic unused_aon_wdog_bark_thold_wdata;
420 logic aon_wdog_bark_thold_regwen;
421
422 always_comb begin
423 1/1 aon_wdog_bark_thold_qs = 32'h0;
Tests: T1 T2 T3
424 1/1 aon_wdog_bark_thold_qs = aon_wdog_bark_thold_qs_int;
Tests: T1 T2 T3
425 end
426
427 prim_reg_cdc #(
428 .DataWidth(32),
429 .ResetVal(32'h0),
430 .BitMask(32'hffffffff),
431 .DstWrReq(0)
432 ) u_wdog_bark_thold_cdc (
433 .clk_src_i (clk_i),
434 .rst_src_ni (rst_ni),
435 .clk_dst_i (clk_aon_i),
436 .rst_dst_ni (rst_aon_ni),
437 .src_regwen_i (wdog_regwen_qs),
438 .src_we_i (wdog_bark_thold_we),
439 .src_re_i ('0),
440 .src_wd_i (reg_wdata[31:0]),
441 .src_busy_o (wdog_bark_thold_busy),
442 .src_qs_o (wdog_bark_thold_qs), // for software read back
443 .dst_update_i ('0),
444 .dst_ds_i ('0),
445 .dst_qs_i (aon_wdog_bark_thold_qs),
446 .dst_we_o (aon_wdog_bark_thold_we),
447 .dst_re_o (),
448 .dst_regwen_o (aon_wdog_bark_thold_regwen),
449 .dst_wd_o (aon_wdog_bark_thold_wdata)
450 );
451 1/1 assign unused_aon_wdog_bark_thold_wdata =
Tests: T1 T2 T3
452 ^aon_wdog_bark_thold_wdata;
453
454 logic [31:0] aon_wdog_bite_thold_qs_int;
455 logic [31:0] aon_wdog_bite_thold_qs;
456 logic [31:0] aon_wdog_bite_thold_wdata;
457 logic aon_wdog_bite_thold_we;
458 logic unused_aon_wdog_bite_thold_wdata;
459 logic aon_wdog_bite_thold_regwen;
460
461 always_comb begin
462 1/1 aon_wdog_bite_thold_qs = 32'h0;
Tests: T1 T2 T3
463 1/1 aon_wdog_bite_thold_qs = aon_wdog_bite_thold_qs_int;
Tests: T1 T2 T3
464 end
465
466 prim_reg_cdc #(
467 .DataWidth(32),
468 .ResetVal(32'h0),
469 .BitMask(32'hffffffff),
470 .DstWrReq(0)
471 ) u_wdog_bite_thold_cdc (
472 .clk_src_i (clk_i),
473 .rst_src_ni (rst_ni),
474 .clk_dst_i (clk_aon_i),
475 .rst_dst_ni (rst_aon_ni),
476 .src_regwen_i (wdog_regwen_qs),
477 .src_we_i (wdog_bite_thold_we),
478 .src_re_i ('0),
479 .src_wd_i (reg_wdata[31:0]),
480 .src_busy_o (wdog_bite_thold_busy),
481 .src_qs_o (wdog_bite_thold_qs), // for software read back
482 .dst_update_i ('0),
483 .dst_ds_i ('0),
484 .dst_qs_i (aon_wdog_bite_thold_qs),
485 .dst_we_o (aon_wdog_bite_thold_we),
486 .dst_re_o (),
487 .dst_regwen_o (aon_wdog_bite_thold_regwen),
488 .dst_wd_o (aon_wdog_bite_thold_wdata)
489 );
490 1/1 assign unused_aon_wdog_bite_thold_wdata =
Tests: T1 T2 T3
491 ^aon_wdog_bite_thold_wdata;
492
493 logic [31:0] aon_wdog_count_ds_int;
494 logic [31:0] aon_wdog_count_qs_int;
495 logic [31:0] aon_wdog_count_ds;
496 logic aon_wdog_count_qe;
497 logic [31:0] aon_wdog_count_qs;
498 logic [31:0] aon_wdog_count_wdata;
499 logic aon_wdog_count_we;
500 logic unused_aon_wdog_count_wdata;
501
502 always_comb begin
503 1/1 aon_wdog_count_qs = 32'h0;
Tests: T1 T2 T3
504 1/1 aon_wdog_count_ds = 32'h0;
Tests: T1 T2 T3
505 1/1 aon_wdog_count_ds = aon_wdog_count_ds_int;
Tests: T1 T2 T3
506 1/1 aon_wdog_count_qs = aon_wdog_count_qs_int;
Tests: T1 T2 T3
507 end
508
509 prim_reg_cdc #(
510 .DataWidth(32),
511 .ResetVal(32'h0),
512 .BitMask(32'hffffffff),
513 .DstWrReq(1)
514 ) u_wdog_count_cdc (
515 .clk_src_i (clk_i),
516 .rst_src_ni (rst_ni),
517 .clk_dst_i (clk_aon_i),
518 .rst_dst_ni (rst_aon_ni),
519 .src_regwen_i ('0),
520 .src_we_i (wdog_count_we),
521 .src_re_i ('0),
522 .src_wd_i (reg_wdata[31:0]),
523 .src_busy_o (wdog_count_busy),
524 .src_qs_o (wdog_count_qs), // for software read back
525 .dst_update_i (aon_wdog_count_qe),
526 .dst_ds_i (aon_wdog_count_ds),
527 .dst_qs_i (aon_wdog_count_qs),
528 .dst_we_o (aon_wdog_count_we),
529 .dst_re_o (),
530 .dst_regwen_o (),
531 .dst_wd_o (aon_wdog_count_wdata)
532 );
533 1/1 assign unused_aon_wdog_count_wdata =
Tests: T1 T2 T3
534 ^aon_wdog_count_wdata;
535
536 logic aon_wkup_cause_ds_int;
537 logic aon_wkup_cause_qs_int;
538 logic [0:0] aon_wkup_cause_ds;
539 logic aon_wkup_cause_qe;
540 logic [0:0] aon_wkup_cause_qs;
541 logic [0:0] aon_wkup_cause_wdata;
542 logic aon_wkup_cause_we;
543 logic unused_aon_wkup_cause_wdata;
544
545 always_comb begin
546 1/1 aon_wkup_cause_qs = 1'h0;
Tests: T2 T3 T4
547 1/1 aon_wkup_cause_ds = 1'h0;
Tests: T2 T3 T4
548 1/1 aon_wkup_cause_ds = aon_wkup_cause_ds_int;
Tests: T2 T3 T4
549 1/1 aon_wkup_cause_qs = aon_wkup_cause_qs_int;
Tests: T2 T3 T4
550 end
551
552 prim_reg_cdc #(
553 .DataWidth(1),
554 .ResetVal(1'h0),
555 .BitMask(1'h1),
556 .DstWrReq(1)
557 ) u_wkup_cause_cdc (
558 .clk_src_i (clk_i),
559 .rst_src_ni (rst_ni),
560 .clk_dst_i (clk_aon_i),
561 .rst_dst_ni (rst_aon_ni),
562 .src_regwen_i ('0),
563 .src_we_i (wkup_cause_we),
564 .src_re_i ('0),
565 .src_wd_i (reg_wdata[0:0]),
566 .src_busy_o (wkup_cause_busy),
567 .src_qs_o (wkup_cause_qs), // for software read back
568 .dst_update_i (aon_wkup_cause_qe),
569 .dst_ds_i (aon_wkup_cause_ds),
570 .dst_qs_i (aon_wkup_cause_qs),
571 .dst_we_o (aon_wkup_cause_we),
572 .dst_re_o (),
573 .dst_regwen_o (),
574 .dst_wd_o (aon_wkup_cause_wdata)
575 );
576 1/1 assign unused_aon_wkup_cause_wdata =
Tests: T1 T2 T3
577 ^aon_wkup_cause_wdata;
578
579 // Register instances
580 // R[alert_test]: V(True)
581 logic alert_test_qe;
582 logic [0:0] alert_test_flds_we;
583 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T20 T21 T22
584 prim_subreg_ext #(
585 .DW (1)
586 ) u_alert_test (
587 .re (1'b0),
588 .we (alert_test_we),
589 .wd (alert_test_wd),
590 .d ('0),
591 .qre (),
592 .qe (alert_test_flds_we[0]),
593 .q (reg2hw.alert_test.q),
594 .ds (),
595 .qs ()
596 );
597 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T20 T21 T22
598
599
600 // R[wkup_ctrl]: V(False)
601 // F[enable]: 0:0
602 prim_subreg #(
603 .DW (1),
604 .SwAccess(prim_subreg_pkg::SwAccessRW),
605 .RESVAL (1'h0),
606 .Mubi (1'b0)
607 ) u_wkup_ctrl_enable (
608 .clk_i (clk_aon_i),
609 .rst_ni (rst_aon_ni),
610
611 // from register interface
612 .we (aon_wkup_ctrl_we),
613 .wd (aon_wkup_ctrl_wdata[0]),
614
615 // from internal hardware
616 .de (1'b0),
617 .d ('0),
618
619 // to internal hardware
620 .qe (),
621 .q (reg2hw.wkup_ctrl.enable.q),
622 .ds (),
623
624 // to register interface (read)
625 .qs (aon_wkup_ctrl_enable_qs_int)
626 );
627
628 // F[prescaler]: 12:1
629 prim_subreg #(
630 .DW (12),
631 .SwAccess(prim_subreg_pkg::SwAccessRW),
632 .RESVAL (12'h0),
633 .Mubi (1'b0)
634 ) u_wkup_ctrl_prescaler (
635 .clk_i (clk_aon_i),
636 .rst_ni (rst_aon_ni),
637
638 // from register interface
639 .we (aon_wkup_ctrl_we),
640 .wd (aon_wkup_ctrl_wdata[12:1]),
641
642 // from internal hardware
643 .de (1'b0),
644 .d ('0),
645
646 // to internal hardware
647 .qe (),
648 .q (reg2hw.wkup_ctrl.prescaler.q),
649 .ds (),
650
651 // to register interface (read)
652 .qs (aon_wkup_ctrl_prescaler_qs_int)
653 );
654
655
656 // R[wkup_thold_hi]: V(False)
657 prim_subreg #(
658 .DW (32),
659 .SwAccess(prim_subreg_pkg::SwAccessRW),
660 .RESVAL (32'h0),
661 .Mubi (1'b0)
662 ) u_wkup_thold_hi (
663 .clk_i (clk_aon_i),
664 .rst_ni (rst_aon_ni),
665
666 // from register interface
667 .we (aon_wkup_thold_hi_we),
668 .wd (aon_wkup_thold_hi_wdata[31:0]),
669
670 // from internal hardware
671 .de (1'b0),
672 .d ('0),
673
674 // to internal hardware
675 .qe (),
676 .q (reg2hw.wkup_thold_hi.q),
677 .ds (),
678
679 // to register interface (read)
680 .qs (aon_wkup_thold_hi_qs_int)
681 );
682
683
684 // R[wkup_thold_lo]: V(False)
685 prim_subreg #(
686 .DW (32),
687 .SwAccess(prim_subreg_pkg::SwAccessRW),
688 .RESVAL (32'h0),
689 .Mubi (1'b0)
690 ) u_wkup_thold_lo (
691 .clk_i (clk_aon_i),
692 .rst_ni (rst_aon_ni),
693
694 // from register interface
695 .we (aon_wkup_thold_lo_we),
696 .wd (aon_wkup_thold_lo_wdata[31:0]),
697
698 // from internal hardware
699 .de (1'b0),
700 .d ('0),
701
702 // to internal hardware
703 .qe (),
704 .q (reg2hw.wkup_thold_lo.q),
705 .ds (),
706
707 // to register interface (read)
708 .qs (aon_wkup_thold_lo_qs_int)
709 );
710
711
712 // R[wkup_count_hi]: V(False)
713 logic [0:0] wkup_count_hi_flds_we;
714 1/1 assign aon_wkup_count_hi_qe = |wkup_count_hi_flds_we;
Tests: T1 T2 T3
715 prim_subreg #(
716 .DW (32),
717 .SwAccess(prim_subreg_pkg::SwAccessRW),
718 .RESVAL (32'h0),
719 .Mubi (1'b0)
720 ) u_wkup_count_hi (
721 .clk_i (clk_aon_i),
722 .rst_ni (rst_aon_ni),
723
724 // from register interface
725 .we (aon_wkup_count_hi_we),
726 .wd (aon_wkup_count_hi_wdata[31:0]),
727
728 // from internal hardware
729 .de (hw2reg.wkup_count_hi.de),
730 .d (hw2reg.wkup_count_hi.d),
731
732 // to internal hardware
733 .qe (wkup_count_hi_flds_we[0]),
734 .q (reg2hw.wkup_count_hi.q),
735 .ds (aon_wkup_count_hi_ds_int),
736
737 // to register interface (read)
738 .qs (aon_wkup_count_hi_qs_int)
739 );
740
741
742 // R[wkup_count_lo]: V(False)
743 logic [0:0] wkup_count_lo_flds_we;
744 1/1 assign aon_wkup_count_lo_qe = |wkup_count_lo_flds_we;
Tests: T1 T2 T3
745 prim_subreg #(
746 .DW (32),
747 .SwAccess(prim_subreg_pkg::SwAccessRW),
748 .RESVAL (32'h0),
749 .Mubi (1'b0)
750 ) u_wkup_count_lo (
751 .clk_i (clk_aon_i),
752 .rst_ni (rst_aon_ni),
753
754 // from register interface
755 .we (aon_wkup_count_lo_we),
756 .wd (aon_wkup_count_lo_wdata[31:0]),
757
758 // from internal hardware
759 .de (hw2reg.wkup_count_lo.de),
760 .d (hw2reg.wkup_count_lo.d),
761
762 // to internal hardware
763 .qe (wkup_count_lo_flds_we[0]),
764 .q (reg2hw.wkup_count_lo.q),
765 .ds (aon_wkup_count_lo_ds_int),
766
767 // to register interface (read)
768 .qs (aon_wkup_count_lo_qs_int)
769 );
770
771
772 // R[wdog_regwen]: V(False)
773 prim_subreg #(
774 .DW (1),
775 .SwAccess(prim_subreg_pkg::SwAccessW0C),
776 .RESVAL (1'h1),
777 .Mubi (1'b0)
778 ) u_wdog_regwen (
779 .clk_i (clk_i),
780 .rst_ni (rst_ni),
781
782 // from register interface
783 .we (wdog_regwen_we),
784 .wd (wdog_regwen_wd),
785
786 // from internal hardware
787 .de (1'b0),
788 .d ('0),
789
790 // to internal hardware
791 .qe (),
792 .q (),
793 .ds (),
794
795 // to register interface (read)
796 .qs (wdog_regwen_qs)
797 );
798
799
800 // R[wdog_ctrl]: V(False)
801 // Create REGWEN-gated WE signal
802 logic aon_wdog_ctrl_gated_we;
803 1/1 assign aon_wdog_ctrl_gated_we = aon_wdog_ctrl_we & aon_wdog_ctrl_regwen;
Tests: T1 T2 T3
804 // F[enable]: 0:0
805 prim_subreg #(
806 .DW (1),
807 .SwAccess(prim_subreg_pkg::SwAccessRW),
808 .RESVAL (1'h0),
809 .Mubi (1'b0)
810 ) u_wdog_ctrl_enable (
811 .clk_i (clk_aon_i),
812 .rst_ni (rst_aon_ni),
813
814 // from register interface
815 .we (aon_wdog_ctrl_gated_we),
816 .wd (aon_wdog_ctrl_wdata[0]),
817
818 // from internal hardware
819 .de (1'b0),
820 .d ('0),
821
822 // to internal hardware
823 .qe (),
824 .q (reg2hw.wdog_ctrl.enable.q),
825 .ds (),
826
827 // to register interface (read)
828 .qs (aon_wdog_ctrl_enable_qs_int)
829 );
830
831 // F[pause_in_sleep]: 1:1
832 prim_subreg #(
833 .DW (1),
834 .SwAccess(prim_subreg_pkg::SwAccessRW),
835 .RESVAL (1'h0),
836 .Mubi (1'b0)
837 ) u_wdog_ctrl_pause_in_sleep (
838 .clk_i (clk_aon_i),
839 .rst_ni (rst_aon_ni),
840
841 // from register interface
842 .we (aon_wdog_ctrl_gated_we),
843 .wd (aon_wdog_ctrl_wdata[1]),
844
845 // from internal hardware
846 .de (1'b0),
847 .d ('0),
848
849 // to internal hardware
850 .qe (),
851 .q (reg2hw.wdog_ctrl.pause_in_sleep.q),
852 .ds (),
853
854 // to register interface (read)
855 .qs (aon_wdog_ctrl_pause_in_sleep_qs_int)
856 );
857
858
859 // R[wdog_bark_thold]: V(False)
860 // Create REGWEN-gated WE signal
861 logic aon_wdog_bark_thold_gated_we;
862 1/1 assign aon_wdog_bark_thold_gated_we = aon_wdog_bark_thold_we & aon_wdog_bark_thold_regwen;
Tests: T1 T2 T3
863 prim_subreg #(
864 .DW (32),
865 .SwAccess(prim_subreg_pkg::SwAccessRW),
866 .RESVAL (32'h0),
867 .Mubi (1'b0)
868 ) u_wdog_bark_thold (
869 .clk_i (clk_aon_i),
870 .rst_ni (rst_aon_ni),
871
872 // from register interface
873 .we (aon_wdog_bark_thold_gated_we),
874 .wd (aon_wdog_bark_thold_wdata[31:0]),
875
876 // from internal hardware
877 .de (1'b0),
878 .d ('0),
879
880 // to internal hardware
881 .qe (),
882 .q (reg2hw.wdog_bark_thold.q),
883 .ds (),
884
885 // to register interface (read)
886 .qs (aon_wdog_bark_thold_qs_int)
887 );
888
889
890 // R[wdog_bite_thold]: V(False)
891 // Create REGWEN-gated WE signal
892 logic aon_wdog_bite_thold_gated_we;
893 1/1 assign aon_wdog_bite_thold_gated_we = aon_wdog_bite_thold_we & aon_wdog_bite_thold_regwen;
Tests: T1 T2 T3
894 prim_subreg #(
895 .DW (32),
896 .SwAccess(prim_subreg_pkg::SwAccessRW),
897 .RESVAL (32'h0),
898 .Mubi (1'b0)
899 ) u_wdog_bite_thold (
900 .clk_i (clk_aon_i),
901 .rst_ni (rst_aon_ni),
902
903 // from register interface
904 .we (aon_wdog_bite_thold_gated_we),
905 .wd (aon_wdog_bite_thold_wdata[31:0]),
906
907 // from internal hardware
908 .de (1'b0),
909 .d ('0),
910
911 // to internal hardware
912 .qe (),
913 .q (reg2hw.wdog_bite_thold.q),
914 .ds (),
915
916 // to register interface (read)
917 .qs (aon_wdog_bite_thold_qs_int)
918 );
919
920
921 // R[wdog_count]: V(False)
922 logic [0:0] wdog_count_flds_we;
923 1/1 assign aon_wdog_count_qe = |wdog_count_flds_we;
Tests: T1 T2 T3
924 prim_subreg #(
925 .DW (32),
926 .SwAccess(prim_subreg_pkg::SwAccessRW),
927 .RESVAL (32'h0),
928 .Mubi (1'b0)
929 ) u_wdog_count (
930 .clk_i (clk_aon_i),
931 .rst_ni (rst_aon_ni),
932
933 // from register interface
934 .we (aon_wdog_count_we),
935 .wd (aon_wdog_count_wdata[31:0]),
936
937 // from internal hardware
938 .de (hw2reg.wdog_count.de),
939 .d (hw2reg.wdog_count.d),
940
941 // to internal hardware
942 .qe (wdog_count_flds_we[0]),
943 .q (reg2hw.wdog_count.q),
944 .ds (aon_wdog_count_ds_int),
945
946 // to register interface (read)
947 .qs (aon_wdog_count_qs_int)
948 );
949
950
951 // R[intr_state]: V(False)
952 // F[wkup_timer_expired]: 0:0
953 prim_subreg #(
954 .DW (1),
955 .SwAccess(prim_subreg_pkg::SwAccessW1C),
956 .RESVAL (1'h0),
957 .Mubi (1'b0)
958 ) u_intr_state_wkup_timer_expired (
959 .clk_i (clk_i),
960 .rst_ni (rst_ni),
961
962 // from register interface
963 .we (intr_state_we),
964 .wd (intr_state_wkup_timer_expired_wd),
965
966 // from internal hardware
967 .de (hw2reg.intr_state.wkup_timer_expired.de),
968 .d (hw2reg.intr_state.wkup_timer_expired.d),
969
970 // to internal hardware
971 .qe (),
972 .q (reg2hw.intr_state.wkup_timer_expired.q),
973 .ds (),
974
975 // to register interface (read)
976 .qs (intr_state_wkup_timer_expired_qs)
977 );
978
979 // F[wdog_timer_bark]: 1:1
980 prim_subreg #(
981 .DW (1),
982 .SwAccess(prim_subreg_pkg::SwAccessW1C),
983 .RESVAL (1'h0),
984 .Mubi (1'b0)
985 ) u_intr_state_wdog_timer_bark (
986 .clk_i (clk_i),
987 .rst_ni (rst_ni),
988
989 // from register interface
990 .we (intr_state_we),
991 .wd (intr_state_wdog_timer_bark_wd),
992
993 // from internal hardware
994 .de (hw2reg.intr_state.wdog_timer_bark.de),
995 .d (hw2reg.intr_state.wdog_timer_bark.d),
996
997 // to internal hardware
998 .qe (),
999 .q (reg2hw.intr_state.wdog_timer_bark.q),
1000 .ds (),
1001
1002 // to register interface (read)
1003 .qs (intr_state_wdog_timer_bark_qs)
1004 );
1005
1006
1007 // R[intr_test]: V(True)
1008 logic intr_test_qe;
1009 logic [1:0] intr_test_flds_we;
1010 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T20 T21 T22
1011 // F[wkup_timer_expired]: 0:0
1012 prim_subreg_ext #(
1013 .DW (1)
1014 ) u_intr_test_wkup_timer_expired (
1015 .re (1'b0),
1016 .we (intr_test_we),
1017 .wd (intr_test_wkup_timer_expired_wd),
1018 .d ('0),
1019 .qre (),
1020 .qe (intr_test_flds_we[0]),
1021 .q (reg2hw.intr_test.wkup_timer_expired.q),
1022 .ds (),
1023 .qs ()
1024 );
1025 1/1 assign reg2hw.intr_test.wkup_timer_expired.qe = intr_test_qe;
Tests: T20 T21 T22
1026
1027 // F[wdog_timer_bark]: 1:1
1028 prim_subreg_ext #(
1029 .DW (1)
1030 ) u_intr_test_wdog_timer_bark (
1031 .re (1'b0),
1032 .we (intr_test_we),
1033 .wd (intr_test_wdog_timer_bark_wd),
1034 .d ('0),
1035 .qre (),
1036 .qe (intr_test_flds_we[1]),
1037 .q (reg2hw.intr_test.wdog_timer_bark.q),
1038 .ds (),
1039 .qs ()
1040 );
1041 1/1 assign reg2hw.intr_test.wdog_timer_bark.qe = intr_test_qe;
Tests: T20 T21 T22
1042
1043
1044 // R[wkup_cause]: V(False)
1045 logic [0:0] wkup_cause_flds_we;
1046 1/1 assign aon_wkup_cause_qe = |wkup_cause_flds_we;
Tests: T1 T2 T3
1047 prim_subreg #(
1048 .DW (1),
1049 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1050 .RESVAL (1'h0),
1051 .Mubi (1'b0)
1052 ) u_wkup_cause (
1053 .clk_i (clk_aon_i),
1054 .rst_ni (rst_aon_ni),
1055
1056 // from register interface
1057 .we (aon_wkup_cause_we),
1058 .wd (aon_wkup_cause_wdata[0]),
1059
1060 // from internal hardware
1061 .de (hw2reg.wkup_cause.de),
1062 .d (hw2reg.wkup_cause.d),
1063
1064 // to internal hardware
1065 .qe (wkup_cause_flds_we[0]),
1066 .q (reg2hw.wkup_cause.q),
1067 .ds (aon_wkup_cause_ds_int),
1068
1069 // to register interface (read)
1070 .qs (aon_wkup_cause_qs_int)
1071 );
1072
1073
1074
1075 logic [13:0] addr_hit;
1076 always_comb begin
1077 1/1 addr_hit = '0;
Tests: T1 T2 T3
1078 1/1 addr_hit[ 0] = (reg_addr == AON_TIMER_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
1079 1/1 addr_hit[ 1] = (reg_addr == AON_TIMER_WKUP_CTRL_OFFSET);
Tests: T1 T2 T3
1080 1/1 addr_hit[ 2] = (reg_addr == AON_TIMER_WKUP_THOLD_HI_OFFSET);
Tests: T1 T2 T3
1081 1/1 addr_hit[ 3] = (reg_addr == AON_TIMER_WKUP_THOLD_LO_OFFSET);
Tests: T1 T2 T3
1082 1/1 addr_hit[ 4] = (reg_addr == AON_TIMER_WKUP_COUNT_HI_OFFSET);
Tests: T1 T2 T3
1083 1/1 addr_hit[ 5] = (reg_addr == AON_TIMER_WKUP_COUNT_LO_OFFSET);
Tests: T1 T2 T3
1084 1/1 addr_hit[ 6] = (reg_addr == AON_TIMER_WDOG_REGWEN_OFFSET);
Tests: T1 T2 T3
1085 1/1 addr_hit[ 7] = (reg_addr == AON_TIMER_WDOG_CTRL_OFFSET);
Tests: T1 T2 T3
1086 1/1 addr_hit[ 8] = (reg_addr == AON_TIMER_WDOG_BARK_THOLD_OFFSET);
Tests: T1 T2 T3
1087 1/1 addr_hit[ 9] = (reg_addr == AON_TIMER_WDOG_BITE_THOLD_OFFSET);
Tests: T1 T2 T3
1088 1/1 addr_hit[10] = (reg_addr == AON_TIMER_WDOG_COUNT_OFFSET);
Tests: T1 T2 T3
1089 1/1 addr_hit[11] = (reg_addr == AON_TIMER_INTR_STATE_OFFSET);
Tests: T1 T2 T3
1090 1/1 addr_hit[12] = (reg_addr == AON_TIMER_INTR_TEST_OFFSET);
Tests: T1 T2 T3
1091 1/1 addr_hit[13] = (reg_addr == AON_TIMER_WKUP_CAUSE_OFFSET);
Tests: T1 T2 T3
1092 end
1093
1094 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
1095
1096 // Check sub-word write is permitted
1097 always_comb begin
1098 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
1099 ((addr_hit[ 0] & (|(AON_TIMER_PERMIT[ 0] & ~reg_be))) |
1100 (addr_hit[ 1] & (|(AON_TIMER_PERMIT[ 1] & ~reg_be))) |
1101 (addr_hit[ 2] & (|(AON_TIMER_PERMIT[ 2] & ~reg_be))) |
1102 (addr_hit[ 3] & (|(AON_TIMER_PERMIT[ 3] & ~reg_be))) |
1103 (addr_hit[ 4] & (|(AON_TIMER_PERMIT[ 4] & ~reg_be))) |
1104 (addr_hit[ 5] & (|(AON_TIMER_PERMIT[ 5] & ~reg_be))) |
1105 (addr_hit[ 6] & (|(AON_TIMER_PERMIT[ 6] & ~reg_be))) |
1106 (addr_hit[ 7] & (|(AON_TIMER_PERMIT[ 7] & ~reg_be))) |
1107 (addr_hit[ 8] & (|(AON_TIMER_PERMIT[ 8] & ~reg_be))) |
1108 (addr_hit[ 9] & (|(AON_TIMER_PERMIT[ 9] & ~reg_be))) |
1109 (addr_hit[10] & (|(AON_TIMER_PERMIT[10] & ~reg_be))) |
1110 (addr_hit[11] & (|(AON_TIMER_PERMIT[11] & ~reg_be))) |
1111 (addr_hit[12] & (|(AON_TIMER_PERMIT[12] & ~reg_be))) |
1112 (addr_hit[13] & (|(AON_TIMER_PERMIT[13] & ~reg_be)))));
1113 end
1114
1115 // Generate write-enables
1116 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
1117
1118 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
1119 1/1 assign wkup_ctrl_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
1120
1121
1122 1/1 assign wkup_thold_hi_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
1123
1124 1/1 assign wkup_thold_lo_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
1125
1126 1/1 assign wkup_count_hi_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
1127
1128 1/1 assign wkup_count_lo_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
1129
1130 1/1 assign wdog_regwen_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
1131
1132 1/1 assign wdog_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
1133 1/1 assign wdog_ctrl_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
1134
1135
1136 1/1 assign wdog_bark_thold_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
1137
1138 1/1 assign wdog_bite_thold_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
1139
1140 1/1 assign wdog_count_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
1141
1142 1/1 assign intr_state_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
1143
1144 1/1 assign intr_state_wkup_timer_expired_wd = reg_wdata[0];
Tests: T1 T2 T3
1145
1146 1/1 assign intr_state_wdog_timer_bark_wd = reg_wdata[1];
Tests: T1 T2 T3
1147 1/1 assign intr_test_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
1148
1149 1/1 assign intr_test_wkup_timer_expired_wd = reg_wdata[0];
Tests: T1 T2 T3
1150
1151 1/1 assign intr_test_wdog_timer_bark_wd = reg_wdata[1];
Tests: T1 T2 T3
1152 1/1 assign wkup_cause_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
1153
1154
1155 // Assign write-enables to checker logic vector.
1156 always_comb begin
1157 1/1 reg_we_check = '0;
Tests: T1 T2 T3
1158 1/1 reg_we_check[0] = alert_test_we;
Tests: T1 T2 T3
1159 1/1 reg_we_check[1] = wkup_ctrl_we;
Tests: T1 T2 T3
1160 1/1 reg_we_check[2] = wkup_thold_hi_we;
Tests: T1 T2 T3
1161 1/1 reg_we_check[3] = wkup_thold_lo_we;
Tests: T1 T2 T3
1162 1/1 reg_we_check[4] = wkup_count_hi_we;
Tests: T1 T2 T3
1163 1/1 reg_we_check[5] = wkup_count_lo_we;
Tests: T1 T2 T3
1164 1/1 reg_we_check[6] = wdog_regwen_we;
Tests: T1 T2 T3
1165 1/1 reg_we_check[7] = wdog_ctrl_we;
Tests: T1 T2 T3
1166 1/1 reg_we_check[8] = wdog_bark_thold_we;
Tests: T1 T2 T3
1167 1/1 reg_we_check[9] = wdog_bite_thold_we;
Tests: T1 T2 T3
1168 1/1 reg_we_check[10] = wdog_count_we;
Tests: T1 T2 T3
1169 1/1 reg_we_check[11] = intr_state_we;
Tests: T1 T2 T3
1170 1/1 reg_we_check[12] = intr_test_we;
Tests: T1 T2 T3
1171 1/1 reg_we_check[13] = wkup_cause_we;
Tests: T1 T2 T3
1172 end
1173
1174 // Read data return
1175 always_comb begin
1176 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
1177 1/1 unique case (1'b1)
Tests: T1 T2 T3
1178 addr_hit[0]: begin
1179 1/1 reg_rdata_next[0] = '0;
Tests: T2 T3 T4
1180 end
1181
1182 addr_hit[1]: begin
1183 1/1 reg_rdata_next = DW'(wkup_ctrl_qs);
Tests: T1 T2 T3
1184 end
1185 addr_hit[2]: begin
1186 1/1 reg_rdata_next = DW'(wkup_thold_hi_qs);
Tests: T1 T2 T3
1187 end
1188 addr_hit[3]: begin
1189 1/1 reg_rdata_next = DW'(wkup_thold_lo_qs);
Tests: T1 T2 T3
1190 end
1191 addr_hit[4]: begin
1192 1/1 reg_rdata_next = DW'(wkup_count_hi_qs);
Tests: T1 T2 T3
1193 end
1194 addr_hit[5]: begin
1195 1/1 reg_rdata_next = DW'(wkup_count_lo_qs);
Tests: T1 T2 T3
1196 end
1197 addr_hit[6]: begin
1198 1/1 reg_rdata_next[0] = wdog_regwen_qs;
Tests: T1 T2 T3
1199 end
1200
1201 addr_hit[7]: begin
1202 1/1 reg_rdata_next = DW'(wdog_ctrl_qs);
Tests: T1 T2 T3
1203 end
1204 addr_hit[8]: begin
1205 1/1 reg_rdata_next = DW'(wdog_bark_thold_qs);
Tests: T1 T2 T3
1206 end
1207 addr_hit[9]: begin
1208 1/1 reg_rdata_next = DW'(wdog_bite_thold_qs);
Tests: T1 T2 T3
1209 end
1210 addr_hit[10]: begin
1211 1/1 reg_rdata_next = DW'(wdog_count_qs);
Tests: T1 T2 T3
1212 end
1213 addr_hit[11]: begin
1214 1/1 reg_rdata_next[0] = intr_state_wkup_timer_expired_qs;
Tests: T1 T2 T3
1215 1/1 reg_rdata_next[1] = intr_state_wdog_timer_bark_qs;
Tests: T1 T2 T3
1216 end
1217
1218 addr_hit[12]: begin
1219 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1220 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
1221 end
1222
1223 addr_hit[13]: begin
1224 1/1 reg_rdata_next = DW'(wkup_cause_qs);
Tests: T1 T2 T3
1225 end
1226 default: begin
1227 reg_rdata_next = '1;
1228 end
1229 endcase
1230 end
1231
1232 // shadow busy
1233 logic shadow_busy;
1234 assign shadow_busy = 1'b0;
1235
1236 // register busy
1237 logic reg_busy_sel;
1238 1/1 assign reg_busy = reg_busy_sel | shadow_busy;
Tests: T1 T2 T3
1239 always_comb begin
1240 1/1 reg_busy_sel = '0;
Tests: T1 T2 T3
1241 1/1 unique case (1'b1)
Tests: T1 T2 T3
1242 addr_hit[1]: begin
1243 1/1 reg_busy_sel = wkup_ctrl_busy;
Tests: T1 T2 T3
1244 end
1245 addr_hit[2]: begin
1246 1/1 reg_busy_sel = wkup_thold_hi_busy;
Tests: T1 T2 T3
1247 end
1248 addr_hit[3]: begin
1249 1/1 reg_busy_sel = wkup_thold_lo_busy;
Tests: T1 T2 T3
1250 end
1251 addr_hit[4]: begin
1252 1/1 reg_busy_sel = wkup_count_hi_busy;
Tests: T1 T2 T3
1253 end
1254 addr_hit[5]: begin
1255 1/1 reg_busy_sel = wkup_count_lo_busy;
Tests: T1 T2 T3
1256 end
1257 addr_hit[7]: begin
1258 1/1 reg_busy_sel = wdog_ctrl_busy;
Tests: T1 T2 T3
1259 end
1260 addr_hit[8]: begin
1261 1/1 reg_busy_sel = wdog_bark_thold_busy;
Tests: T1 T2 T3
1262 end
1263 addr_hit[9]: begin
1264 1/1 reg_busy_sel = wdog_bite_thold_busy;
Tests: T1 T2 T3
1265 end
1266 addr_hit[10]: begin
1267 1/1 reg_busy_sel = wdog_count_busy;
Tests: T1 T2 T3
1268 end
1269 addr_hit[13]: begin
1270 1/1 reg_busy_sel = wkup_cause_busy;
Tests: T1 T2 T3
1271 end
1272 default: begin
1273 reg_busy_sel = '0;
1274 end
1275 endcase
1276 end
1277
1278
1279 // Unused signal tieoff
1280
1281 // wdata / byte enable are not always fully used
1282 // add a blanket unused statement to handle lint waivers
1283 logic unused_wdata;
1284 logic unused_be;
1285 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
1286 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg
| Total | Covered | Percent |
|---|
| Conditions | 171 | 171 | 100.00 |
| Logical | 171 | 171 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T11,T25,T26 |
| 1 | 0 | Covered | T36,T39,T40 |
LINE 79
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T11,T25,T26 |
| 0 | 1 | 0 | Covered | T36,T39,T40 |
| 1 | 0 | 0 | Covered | T11,T25,T26 |
LINE 121
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T36,T39,T40 |
| 0 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 0 | 0 | Covered | T20,T21,T22 |
LINE 803
EXPRESSION (aon_wdog_ctrl_we & aon_wdog_ctrl_regwen)
--------1------- ----------2---------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T3,T4,T6 |
| 1 | 1 | Covered | T1,T2,T5 |
LINE 862
EXPRESSION (aon_wdog_bark_thold_we & aon_wdog_bark_thold_regwen)
-----------1---------- -------------2------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T20,T21,T27 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 893
EXPRESSION (aon_wdog_bite_thold_we & aon_wdog_bite_thold_regwen)
-----------1---------- -------------2------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T20,T21,T27 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1078
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_ALERT_TEST_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T16 |
LINE 1079
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CTRL_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1080
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_THOLD_HI_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1081
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_THOLD_LO_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1082
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_COUNT_HI_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1083
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_COUNT_LO_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1084
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_REGWEN_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1085
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_CTRL_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1086
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BARK_THOLD_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1087
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BITE_THOLD_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1088
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_COUNT_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1089
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_STATE_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1090
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_TEST_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T24 |
LINE 1091
EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CAUSE_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1094
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1094
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 1098
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 1098
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))))
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Covered | T1,T16,T18 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T1,T3,T17 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T1,T16,T19 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T1,T24,T16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T24 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T24,T16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T16,T17,T19 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T24,T17 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T24 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T24,T16 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T24 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T24,T16,T17 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T24,T16,T18 |
LINE 1098
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T17,T20 |
| 1 | 1 | Covered | T24,T16,T18 |
LINE 1098
SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T24,T16,T17 |
LINE 1098
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T24 |
LINE 1098
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T24,T16 |
LINE 1098
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T24 |
LINE 1098
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T24,T17 |
LINE 1098
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T16,T17,T19 |
LINE 1098
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T24,T16 |
LINE 1098
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T24 |
LINE 1098
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T24,T16 |
LINE 1098
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T16,T19 |
LINE 1098
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T24 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1098
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T24,T16 |
| 1 | 1 | Covered | T1,T3,T17 |
LINE 1098
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T16,T18 |
LINE 1116
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T24,T16 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T36,T41,T42 |
LINE 1119
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1122
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1124
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1126
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1128
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1130
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1133
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1136
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1138
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1140
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1142
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1147
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T3,T24 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T20,T27,T43 |
LINE 1152
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1238
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg
| Line No. | Total | Covered | Percent |
| Branches |
|
31 |
31 |
100.00 |
| TERNARY |
1094 |
2 |
2 |
100.00 |
| IF |
70 |
3 |
3 |
100.00 |
| CASE |
1177 |
15 |
15 |
100.00 |
| CASE |
1241 |
11 |
11 |
100.00 |
1094 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
70 if (!rst_ni) begin
-1-
71 err_q <= '0;
==>
72 end else if (intg_err || reg_we_err) begin
-2-
73 err_q <= 1'b1;
==>
74 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T11,T25,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
1177 unique case (1'b1)
-1-
1178 addr_hit[0]: begin
1179 reg_rdata_next[0] = '0;
==>
1180 end
1181
1182 addr_hit[1]: begin
1183 reg_rdata_next = DW'(wkup_ctrl_qs);
==>
1184 end
1185 addr_hit[2]: begin
1186 reg_rdata_next = DW'(wkup_thold_hi_qs);
==>
1187 end
1188 addr_hit[3]: begin
1189 reg_rdata_next = DW'(wkup_thold_lo_qs);
==>
1190 end
1191 addr_hit[4]: begin
1192 reg_rdata_next = DW'(wkup_count_hi_qs);
==>
1193 end
1194 addr_hit[5]: begin
1195 reg_rdata_next = DW'(wkup_count_lo_qs);
==>
1196 end
1197 addr_hit[6]: begin
1198 reg_rdata_next[0] = wdog_regwen_qs;
==>
1199 end
1200
1201 addr_hit[7]: begin
1202 reg_rdata_next = DW'(wdog_ctrl_qs);
==>
1203 end
1204 addr_hit[8]: begin
1205 reg_rdata_next = DW'(wdog_bark_thold_qs);
==>
1206 end
1207 addr_hit[9]: begin
1208 reg_rdata_next = DW'(wdog_bite_thold_qs);
==>
1209 end
1210 addr_hit[10]: begin
1211 reg_rdata_next = DW'(wdog_count_qs);
==>
1212 end
1213 addr_hit[11]: begin
1214 reg_rdata_next[0] = intr_state_wkup_timer_expired_qs;
==>
1215 reg_rdata_next[1] = intr_state_wdog_timer_bark_qs;
1216 end
1217
1218 addr_hit[12]: begin
1219 reg_rdata_next[0] = '0;
==>
1220 reg_rdata_next[1] = '0;
1221 end
1222
1223 addr_hit[13]: begin
1224 reg_rdata_next = DW'(wkup_cause_qs);
==>
1225 end
1226 default: begin
1227 reg_rdata_next = '1;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[0] |
Covered |
T2,T3,T4 |
| addr_hit[1] |
Covered |
T1,T2,T3 |
| addr_hit[2] |
Covered |
T1,T2,T3 |
| addr_hit[3] |
Covered |
T1,T2,T3 |
| addr_hit[4] |
Covered |
T1,T2,T3 |
| addr_hit[5] |
Covered |
T1,T2,T3 |
| addr_hit[6] |
Covered |
T1,T2,T3 |
| addr_hit[7] |
Covered |
T1,T2,T3 |
| addr_hit[8] |
Covered |
T1,T2,T3 |
| addr_hit[9] |
Covered |
T1,T2,T3 |
| addr_hit[10] |
Covered |
T1,T2,T3 |
| addr_hit[11] |
Covered |
T1,T2,T3 |
| addr_hit[12] |
Covered |
T1,T2,T3 |
| addr_hit[13] |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
1241 unique case (1'b1)
-1-
1242 addr_hit[1]: begin
1243 reg_busy_sel = wkup_ctrl_busy;
==>
1244 end
1245 addr_hit[2]: begin
1246 reg_busy_sel = wkup_thold_hi_busy;
==>
1247 end
1248 addr_hit[3]: begin
1249 reg_busy_sel = wkup_thold_lo_busy;
==>
1250 end
1251 addr_hit[4]: begin
1252 reg_busy_sel = wkup_count_hi_busy;
==>
1253 end
1254 addr_hit[5]: begin
1255 reg_busy_sel = wkup_count_lo_busy;
==>
1256 end
1257 addr_hit[7]: begin
1258 reg_busy_sel = wdog_ctrl_busy;
==>
1259 end
1260 addr_hit[8]: begin
1261 reg_busy_sel = wdog_bark_thold_busy;
==>
1262 end
1263 addr_hit[9]: begin
1264 reg_busy_sel = wdog_bite_thold_busy;
==>
1265 end
1266 addr_hit[10]: begin
1267 reg_busy_sel = wdog_count_busy;
==>
1268 end
1269 addr_hit[13]: begin
1270 reg_busy_sel = wkup_cause_busy;
==>
1271 end
1272 default: begin
1273 reg_busy_sel = '0;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[1] |
Covered |
T1,T2,T3 |
| addr_hit[2] |
Covered |
T1,T2,T3 |
| addr_hit[3] |
Covered |
T1,T2,T3 |
| addr_hit[4] |
Covered |
T1,T2,T3 |
| addr_hit[5] |
Covered |
T1,T2,T3 |
| addr_hit[7] |
Covered |
T1,T2,T3 |
| addr_hit[8] |
Covered |
T1,T2,T3 |
| addr_hit[9] |
Covered |
T1,T2,T3 |
| addr_hit[10] |
Covered |
T1,T2,T3 |
| addr_hit[13] |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg
Assertion Details
en2addrHit
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
517111313 |
75702 |
0 |
0 |
| T1 |
2792 |
19 |
0 |
0 |
| T2 |
9291 |
22 |
0 |
0 |
| T3 |
10866 |
18 |
0 |
0 |
| T4 |
6752 |
22 |
0 |
0 |
| T5 |
11274 |
19 |
0 |
0 |
| T6 |
39008 |
18 |
0 |
0 |
| T7 |
53258 |
22 |
0 |
0 |
| T8 |
3101 |
22 |
0 |
0 |
| T9 |
39727 |
18 |
0 |
0 |
| T10 |
0 |
19 |
0 |
0 |
| T11 |
56557 |
0 |
0 |
0 |
reAfterRv
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
517111313 |
75702 |
0 |
0 |
| T1 |
2792 |
19 |
0 |
0 |
| T2 |
9291 |
22 |
0 |
0 |
| T3 |
10866 |
18 |
0 |
0 |
| T4 |
6752 |
22 |
0 |
0 |
| T5 |
11274 |
19 |
0 |
0 |
| T6 |
39008 |
18 |
0 |
0 |
| T7 |
53258 |
22 |
0 |
0 |
| T8 |
3101 |
22 |
0 |
0 |
| T9 |
39727 |
18 |
0 |
0 |
| T10 |
0 |
19 |
0 |
0 |
| T11 |
56557 |
0 |
0 |
0 |
rePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
517111313 |
20860 |
0 |
0 |
| T1 |
2792 |
1 |
0 |
0 |
| T2 |
9291 |
1 |
0 |
0 |
| T3 |
10866 |
1 |
0 |
0 |
| T4 |
6752 |
1 |
0 |
0 |
| T5 |
11274 |
1 |
0 |
0 |
| T6 |
39008 |
1 |
0 |
0 |
| T7 |
53258 |
1 |
0 |
0 |
| T8 |
3101 |
1 |
0 |
0 |
| T9 |
39727 |
1 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
56557 |
0 |
0 |
0 |
wePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
517111313 |
54842 |
0 |
0 |
| T1 |
2792 |
18 |
0 |
0 |
| T2 |
9291 |
21 |
0 |
0 |
| T3 |
10866 |
17 |
0 |
0 |
| T4 |
6752 |
21 |
0 |
0 |
| T5 |
11274 |
18 |
0 |
0 |
| T6 |
39008 |
17 |
0 |
0 |
| T7 |
53258 |
21 |
0 |
0 |
| T8 |
3101 |
21 |
0 |
0 |
| T9 |
39727 |
17 |
0 |
0 |
| T10 |
0 |
18 |
0 |
0 |
| T11 |
56557 |
0 |
0 |
0 |