Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	594021975	299349	0	0
wdog_bark_thold_rd_A	594021975	6129	0	0
wdog_bite_thold_rd_A	594021975	5734	0	0
wdog_ctrl_rd_A	594021975	5796	0	0
wdog_regwen_rd_A	594021975	6144	0	0
wkup_ctrl_rd_A	594021975	5380	0	0
wkup_thold_hi_rd_A	594021975	6357	0	0
wkup_thold_lo_rd_A	594021975	5589	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594021975	299349	0	0
T6	249077	4784	0	0
T7	10247	0	0	0
T8	430106	0	0	0
T9	23936	0	0	0
T10	9235	0	0	0
T12	170839	0	0	0
T13	431240	7151	0	0
T14	0	781	0	0
T15	38239	0	0	0
T30	0	3448	0	0
T32	0	9323	0	0
T33	0	7072	0	0
T34	0	3640	0	0
T35	0	10836	0	0
T36	0	7244	0	0
T37	0	2400	0	0
T38	53025	0	0	0
T39	336551	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594021975	6129	0	0
T13	431240	775	0	0
T14	74080	0	0	0
T15	38239	0	0	0
T20	148468	0	0	0
T22	13234	0	0	0
T23	43256	0	0	0
T33	0	409	0	0
T36	0	806	0	0
T38	53025	0	0	0
T39	336551	0	0	0
T68	0	261	0	0
T69	0	786	0	0
T70	0	444	0	0
T71	0	192	0	0
T72	0	243	0	0
T73	0	953	0	0
T74	0	110	0	0
T75	227708	0	0	0
T76	30989	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594021975	5734	0	0
T13	431240	751	0	0
T14	74080	0	0	0
T15	38239	0	0	0
T20	148468	0	0	0
T22	13234	0	0	0
T23	43256	0	0	0
T33	0	320	0	0
T36	0	804	0	0
T38	53025	0	0	0
T39	336551	0	0	0
T68	0	269	0	0
T69	0	774	0	0
T70	0	362	0	0
T71	0	153	0	0
T72	0	323	0	0
T73	0	823	0	0
T74	0	75	0	0
T75	227708	0	0	0
T76	30989	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594021975	5796	0	0
T13	431240	763	0	0
T14	74080	0	0	0
T15	38239	0	0	0
T20	148468	0	0	0
T22	13234	0	0	0
T23	43256	0	0	0
T33	0	371	0	0
T36	0	692	0	0
T38	53025	0	0	0
T39	336551	0	0	0
T68	0	194	0	0
T69	0	796	0	0
T70	0	403	0	0
T71	0	144	0	0
T72	0	279	0	0
T73	0	788	0	0
T74	0	62	0	0
T75	227708	0	0	0
T76	30989	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594021975	6144	0	0
T13	431240	785	0	0
T14	74080	0	0	0
T15	38239	0	0	0
T20	148468	0	0	0
T22	13234	0	0	0
T23	43256	0	0	0
T33	0	423	0	0
T36	0	663	0	0
T38	53025	0	0	0
T39	336551	0	0	0
T68	0	363	0	0
T69	0	804	0	0
T70	0	411	0	0
T71	0	117	0	0
T72	0	314	0	0
T73	0	803	0	0
T74	0	85	0	0
T75	227708	0	0	0
T76	30989	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594021975	5380	0	0
T13	431240	707	0	0
T14	74080	0	0	0
T15	38239	0	0	0
T20	148468	0	0	0
T22	13234	0	0	0
T23	43256	0	0	0
T33	0	309	0	0
T36	0	556	0	0
T38	53025	0	0	0
T39	336551	0	0	0
T68	0	204	0	0
T69	0	679	0	0
T70	0	434	0	0
T71	0	155	0	0
T72	0	321	0	0
T73	0	741	0	0
T74	0	59	0	0
T75	227708	0	0	0
T76	30989	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594021975	6357	0	0
T13	431240	775	0	0
T14	74080	0	0	0
T15	38239	0	0	0
T20	148468	0	0	0
T22	13234	0	0	0
T23	43256	0	0	0
T33	0	433	0	0
T36	0	762	0	0
T38	53025	0	0	0
T39	336551	0	0	0
T68	0	243	0	0
T69	0	888	0	0
T70	0	515	0	0
T71	0	134	0	0
T72	0	337	0	0
T73	0	892	0	0
T74	0	89	0	0
T75	227708	0	0	0
T76	30989	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594021975	5589	0	0
T13	431240	708	0	0
T14	74080	0	0	0
T15	38239	0	0	0
T20	148468	0	0	0
T22	13234	0	0	0
T23	43256	0	0	0
T33	0	384	0	0
T36	0	656	0	0
T38	53025	0	0	0
T39	336551	0	0	0
T68	0	218	0	0
T69	0	715	0	0
T70	0	368	0	0
T71	0	180	0	0
T72	0	280	0	0
T73	0	820	0	0
T74	0	56	0	0
T75	227708	0	0	0
T76	30989	0	0	0