Unified Coverage Report :: Module :: aon_timer

Module : aon_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	66.67	100.00		100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.00	100.00	80.00	100.00		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00	100.00	80.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	99.33	95.61	100.00		98.40	99.51

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
aon_timer_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_aon_intr_flop	100.00	100.00				100.00
u_core	100.00	100.00	100.00			100.00
u_intr_hw	100.00	100.00				100.00	100.00
u_intr_sync	100.00	100.00				100.00
u_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_reg	98.26	99.26	95.74	100.00		98.30	98.00
u_sync_sleep_mode	100.00	100.00				100.00

Line Coverage for Module : aon_timer

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	244	3	3	100.00
CONT_ASSIGN	251	1	1	100.00

80                      
81         1/1            assign hw2reg.wkup_count_lo.de = aon_wkup_count_reg_wr;
           Tests:       T1 T2 T3 
82         1/1            assign hw2reg.wkup_count_hi.de = aon_wkup_count_reg_wr;
           Tests:       T1 T2 T3 
83         1/1            assign hw2reg.wkup_count_lo.d  = aon_wkup_count_wr_data[31:0];
           Tests:       T1 T2 T3 
84         1/1            assign hw2reg.wkup_count_hi.d  = aon_wkup_count_wr_data[63:32];
           Tests:       T2 T6 T7 
85         1/1            assign hw2reg.wdog_count.de = aon_wdog_count_reg_wr;
           Tests:       T1 T6 T7 
86         1/1            assign hw2reg.wdog_count.d  = aon_wdog_count_wr_data;
           Tests:       T1 T2 T4 
87                      
88                        // registers instantiation
89                        aon_timer_reg_top u_reg (
90                          .clk_i,
91                          .rst_ni,
92                          .clk_aon_i,
93                          .rst_aon_ni,
94                      
95                          .tl_i,
96                          .tl_o,
97                      
98                          .reg2hw,
99                          .hw2reg,
100                     
101                         // SEC_CM: BUS.INTEGRITY
102                         .intg_err_o (alerts[0])
103                       );
104                     
105                       ////////////
106                       // Alerts //
107                       ////////////
108                     
109        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
110                         reg2hw.alert_test.q &
111                         reg2hw.alert_test.qe
112                       };
113                     
114                       for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
115                         prim_alert_sender #(
116                           .AsyncOn(AlertAsyncOn[i]),
117                           .IsFatal(1'b1)
118                         ) u_prim_alert_sender (
119                           .clk_i,
120                           .rst_ni,
121                           .alert_test_i  ( alert_test[i] ),
122                           .alert_req_i   ( alerts[0]     ),
123                           .alert_ack_o   (               ),
124                           .alert_state_o (               ),
125                           .alert_rx_i    ( alert_rx_i[i] ),
126                           .alert_tx_o    ( alert_tx_o[i] )
127                         );
128                       end
129                     
130                       // Lifecycle sync
131                       prim_lc_sync #(
132                         .NumCopies(3)
133                       ) u_lc_sync_escalate_en (
134                         .clk_i   (clk_aon_i),
135                         .rst_ni  (rst_aon_ni),
136                         .lc_en_i (lc_escalate_en_i),
137                         .lc_en_o (lc_escalate_en)
138                       );
139                     
140                       ////////////////
141                       // Timer Core //
142                       ////////////////
143                     
144                       aon_timer_core u_core (
145                         .clk_aon_i,
146                         .rst_aon_ni,
147                         .sleep_mode_i              (aon_sleep_mode),
148                         .lc_escalate_en_i          (lc_escalate_en),
149                         .reg2hw_i                  (reg2hw),
150                         .wkup_count_reg_wr_o       (aon_wkup_count_reg_wr),
151                         .wkup_count_wr_data_o      (aon_wkup_count_wr_data),
152                         .wdog_count_reg_wr_o       (aon_wdog_count_reg_wr),
153                         .wdog_count_wr_data_o      (aon_wdog_count_wr_data),
154                         .wkup_intr_o               (aon_wkup_intr_set),
155                         .wdog_intr_o               (aon_wdog_intr_set),
156                         .wdog_reset_req_o          (aon_rst_req_set)
157                       );
158                     
159                       ////////////////////
160                       // Wakeup Signals //
161                       ////////////////////
162                     
163                       // Wakeup request is set by HW and cleared by SW
164                       // The wakeup cause is always captured and only sent out when the system has entered sleep mode
165        1/1            assign hw2reg.wkup_cause.de = aon_wkup_intr_set | aon_wdog_intr_set;
           Tests:       T1 T2 T3 
166                       assign hw2reg.wkup_cause.d  = 1'b1;
167                     
168                       // cause register resides in AON domain.
169        1/1            assign wkup_req_o = reg2hw.wkup_cause.q;
           Tests:       T1 T2 T3 
170                     
171                       ////////////////////////
172                       // Interrupt Handling //
173                       ////////////////////////
174                     
175                       logic [1:0] aon_intr_set, intr_set;
176                     
177                       prim_flop #(
178                         .Width      (2),
179                         .ResetValue (2'b 00)
180                       ) u_aon_intr_flop (
181                         .clk_i  (clk_aon_i),
182                         .rst_ni (rst_aon_ni),
183                         .d_i    ({aon_wdog_intr_set, aon_wkup_intr_set}),
184                         .q_o    (aon_intr_set)
185                       );
186                     
187                       prim_edge_detector #(
188                         .Width      (2),
189                         .ResetValue (2'b 00),
190                         .EnSync     (1'b 1)
191                       ) u_intr_sync (
192                         .clk_i,
193                         .rst_ni,
194                         .d_i               (aon_intr_set),
195                         .q_sync_o          (),
196                         .q_posedge_pulse_o (intr_set),
197                         .q_negedge_pulse_o ()
198                       );
199                     
200                       // Registers to interrupt
201        1/1            assign intr_test_qe           = reg2hw.intr_test.wkup_timer_expired.qe |
           Tests:       T6 T13 T14 
202                                                       reg2hw.intr_test.wdog_timer_bark.qe;
203        1/1            assign intr_test_q [AON_WKUP] = reg2hw.intr_test.wkup_timer_expired.q;
           Tests:       T1 T2 T3 
204        1/1            assign intr_state_q[AON_WKUP] = reg2hw.intr_state.wkup_timer_expired.q;
           Tests:       T1 T2 T3 
205        1/1            assign intr_test_q [AON_WDOG] = reg2hw.intr_test.wdog_timer_bark.q;
           Tests:       T1 T2 T3 
206        1/1            assign intr_state_q[AON_WDOG] = reg2hw.intr_state.wdog_timer_bark.q;
           Tests:       T1 T2 T3 
207                     
208                       // Interrupts to registers
209        1/1            assign hw2reg.intr_state.wkup_timer_expired.d  = intr_state_d[AON_WKUP];
           Tests:       T1 T2 T3 
210        1/1            assign hw2reg.intr_state.wkup_timer_expired.de = intr_state_de;
           Tests:       T1 T2 T3 
211        1/1            assign hw2reg.intr_state.wdog_timer_bark.d  = intr_state_d[AON_WDOG];
           Tests:       T1 T2 T3 
212        1/1            assign hw2reg.intr_state.wdog_timer_bark.de = intr_state_de;
           Tests:       T1 T2 T3 
213                     
214                       prim_intr_hw #(
215                         .Width (2)
216                       ) u_intr_hw (
217                         .clk_i,
218                         .rst_ni,
219                         .event_intr_i           (intr_set),
220                         .reg2hw_intr_enable_q_i (2'b11),
221                         .reg2hw_intr_test_q_i   (intr_test_q),
222                         .reg2hw_intr_test_qe_i  (intr_test_qe),
223                         .reg2hw_intr_state_q_i  (intr_state_q),
224                         .hw2reg_intr_state_de_o (intr_state_de),
225                         .hw2reg_intr_state_d_o  (intr_state_d),
226                     
227                         .intr_o                 (intr_out)
228                       );
229                     
230        1/1            assign intr_wkup_timer_expired_o = intr_out[AON_WKUP];
           Tests:       T1 T2 T3 
231        1/1            assign intr_wdog_timer_bark_o = intr_out[AON_WDOG];
           Tests:       T1 T2 T3 
232                     
233                       // The interrupt line can be routed as nmi as well.
234        1/1            assign nmi_wdog_timer_bark_o = intr_wdog_timer_bark_o;
           Tests:       T1 T2 T3 
235                     
236                       ///////////////////
237                       // Reset Request //
238                       ///////////////////
239                     
240                       // Once set, the reset request remains asserted until the next aon reset
241        1/1            assign aon_rst_req_d = aon_rst_req_set | aon_rst_req_q;
           Tests:       T1 T6 T9 
242                     
243                       always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
244        1/1              if (!rst_aon_ni) begin
           Tests:       T1 T2 T3 
245        1/1                aon_rst_req_q <= 1'b0;
           Tests:       T1 T2 T3 
246                         end else begin
247        1/1                aon_rst_req_q <= aon_rst_req_d;
           Tests:       T1 T2 T3 
248                         end
249                       end
250                     
251        1/1            assign aon_timer_rst_req_o = aon_rst_req_q;
           Tests:       T6 T10 T13 

---

Cond Coverage for Module : aon_timer

	Total	Covered	Percent
Conditions	12	8	66.67
Logical	12	8	66.67
Non-Logical	0	0
Event	0	0

 LINE       109
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       165
 EXPRESSION (aon_wkup_intr_set | aon_wdog_intr_set)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T13
1	0	Covered	T2,T3,T4

 LINE       201
 EXPRESSION (reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe)
             -------------------1------------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       241
 EXPRESSION (aon_rst_req_set | aon_rst_req_q)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T13
1	0	Covered	T6,T10,T13

---

Toggle Coverage for Module : aon_timer

	Total	Covered	Percent
Totals	35	35	100.00
Total Bits	356	356	100.00
Total Bits 0->1	178	178	100.00
Total Bits 1->0	178	178	100.00

Ports	35	35	100.00
Port Bits	356	356	100.00
Port Bits 0->1	178	178	100.00
Port Bits 1->0	178	178	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T11,T6,T12	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T11,T6,T12	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T11	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T11,T4	Yes	T2,T11,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T11,T4	Yes	T2,T11,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T11,T4	Yes	T2,T11,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T6,T13,T14	Yes	T6,T13,T14	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T6,T13	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T11,T12,T15	Yes	T11,T12,T15	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T11,T12,T15	Yes	T11,T12,T15	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T1,T5,T6	Yes	T16,T17,T18	INPUT
intr_wkup_timer_expired_o	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	OUTPUT
wkup_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T6,T13,T16	Yes	T6,T10,T13	OUTPUT
sleep_mode_i	Yes	Yes	T1,T2,T3	Yes	T17,T18,T19	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : aon_timer

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	244	2	2	100.00

244            if (!rst_aon_ni) begin
               -1-  
245              aon_rst_req_q <= 1'b0;
                 ==>
246            end else begin
247              aon_rst_req_q <= aon_rst_req_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : aon_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	579185241	579046059	0	0
FpvSecCmRegWeOnehotCheck_A	579185241	70	0	0
IntrWdogKnown_A	579185241	579046059	0	0
IntrWkupKnown_A	579185241	579046059	0	0
RstReqKnown_A	2235752	2180436	0	0
TlOAReadyKnown_A	579185241	579046059	0	0
TlODValidKnown_A	579185241	579046059	0	0
WkupReqKnown_A	2235752	2180436	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	70	0	0
T4	14618	0	0	0
T5	97066	0	0	0
T6	249077	0	0	0
T7	10247	0	0	0
T8	430106	0	0	0
T9	23936	0	0	0
T10	9235	0	0	0
T11	90582	10	0	0
T12	170839	10	0	0
T13	431240	0	0	0
T15	0	10	0	0
T20	0	20	0	0
T21	0	20	0	0

IntrWdogKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

IntrWkupKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

RstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2235752	2180436	0	0
T1	116	29	0	0
T2	129	36	0	0
T3	4611	4555	0	0
T4	116	25	0	0
T5	238	152	0	0
T6	507	397	0	0
T7	81	19	0	0
T8	4778	4690	0	0
T11	861	12	0	0
T12	775	5	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

WkupReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2235752	2180436	0	0
T1	116	29	0	0
T2	129	36	0	0
T3	4611	4555	0	0
T4	116	25	0	0
T5	238	152	0	0
T6	507	397	0	0
T7	81	19	0	0
T8	4778	4690	0	0
T11	861	12	0	0
T12	775	5	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	244	3	3	100.00
CONT_ASSIGN	251	1	1	100.00

80                      
81         1/1            assign hw2reg.wkup_count_lo.de = aon_wkup_count_reg_wr;
           Tests:       T1 T2 T3 
82         1/1            assign hw2reg.wkup_count_hi.de = aon_wkup_count_reg_wr;
           Tests:       T1 T2 T3 
83         1/1            assign hw2reg.wkup_count_lo.d  = aon_wkup_count_wr_data[31:0];
           Tests:       T1 T2 T3 
84         1/1            assign hw2reg.wkup_count_hi.d  = aon_wkup_count_wr_data[63:32];
           Tests:       T2 T6 T7 
85         1/1            assign hw2reg.wdog_count.de = aon_wdog_count_reg_wr;
           Tests:       T1 T6 T7 
86         1/1            assign hw2reg.wdog_count.d  = aon_wdog_count_wr_data;
           Tests:       T1 T2 T4 
87                      
88                        // registers instantiation
89                        aon_timer_reg_top u_reg (
90                          .clk_i,
91                          .rst_ni,
92                          .clk_aon_i,
93                          .rst_aon_ni,
94                      
95                          .tl_i,
96                          .tl_o,
97                      
98                          .reg2hw,
99                          .hw2reg,
100                     
101                         // SEC_CM: BUS.INTEGRITY
102                         .intg_err_o (alerts[0])
103                       );
104                     
105                       ////////////
106                       // Alerts //
107                       ////////////
108                     
109        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
110                         reg2hw.alert_test.q &
111                         reg2hw.alert_test.qe
112                       };
113                     
114                       for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
115                         prim_alert_sender #(
116                           .AsyncOn(AlertAsyncOn[i]),
117                           .IsFatal(1'b1)
118                         ) u_prim_alert_sender (
119                           .clk_i,
120                           .rst_ni,
121                           .alert_test_i  ( alert_test[i] ),
122                           .alert_req_i   ( alerts[0]     ),
123                           .alert_ack_o   (               ),
124                           .alert_state_o (               ),
125                           .alert_rx_i    ( alert_rx_i[i] ),
126                           .alert_tx_o    ( alert_tx_o[i] )
127                         );
128                       end
129                     
130                       // Lifecycle sync
131                       prim_lc_sync #(
132                         .NumCopies(3)
133                       ) u_lc_sync_escalate_en (
134                         .clk_i   (clk_aon_i),
135                         .rst_ni  (rst_aon_ni),
136                         .lc_en_i (lc_escalate_en_i),
137                         .lc_en_o (lc_escalate_en)
138                       );
139                     
140                       ////////////////
141                       // Timer Core //
142                       ////////////////
143                     
144                       aon_timer_core u_core (
145                         .clk_aon_i,
146                         .rst_aon_ni,
147                         .sleep_mode_i              (aon_sleep_mode),
148                         .lc_escalate_en_i          (lc_escalate_en),
149                         .reg2hw_i                  (reg2hw),
150                         .wkup_count_reg_wr_o       (aon_wkup_count_reg_wr),
151                         .wkup_count_wr_data_o      (aon_wkup_count_wr_data),
152                         .wdog_count_reg_wr_o       (aon_wdog_count_reg_wr),
153                         .wdog_count_wr_data_o      (aon_wdog_count_wr_data),
154                         .wkup_intr_o               (aon_wkup_intr_set),
155                         .wdog_intr_o               (aon_wdog_intr_set),
156                         .wdog_reset_req_o          (aon_rst_req_set)
157                       );
158                     
159                       ////////////////////
160                       // Wakeup Signals //
161                       ////////////////////
162                     
163                       // Wakeup request is set by HW and cleared by SW
164                       // The wakeup cause is always captured and only sent out when the system has entered sleep mode
165        1/1            assign hw2reg.wkup_cause.de = aon_wkup_intr_set | aon_wdog_intr_set;
           Tests:       T1 T2 T3 
166                       assign hw2reg.wkup_cause.d  = 1'b1;
167                     
168                       // cause register resides in AON domain.
169        1/1            assign wkup_req_o = reg2hw.wkup_cause.q;
           Tests:       T1 T2 T3 
170                     
171                       ////////////////////////
172                       // Interrupt Handling //
173                       ////////////////////////
174                     
175                       logic [1:0] aon_intr_set, intr_set;
176                     
177                       prim_flop #(
178                         .Width      (2),
179                         .ResetValue (2'b 00)
180                       ) u_aon_intr_flop (
181                         .clk_i  (clk_aon_i),
182                         .rst_ni (rst_aon_ni),
183                         .d_i    ({aon_wdog_intr_set, aon_wkup_intr_set}),
184                         .q_o    (aon_intr_set)
185                       );
186                     
187                       prim_edge_detector #(
188                         .Width      (2),
189                         .ResetValue (2'b 00),
190                         .EnSync     (1'b 1)
191                       ) u_intr_sync (
192                         .clk_i,
193                         .rst_ni,
194                         .d_i               (aon_intr_set),
195                         .q_sync_o          (),
196                         .q_posedge_pulse_o (intr_set),
197                         .q_negedge_pulse_o ()
198                       );
199                     
200                       // Registers to interrupt
201        1/1            assign intr_test_qe           = reg2hw.intr_test.wkup_timer_expired.qe |
           Tests:       T6 T13 T14 
202                                                       reg2hw.intr_test.wdog_timer_bark.qe;
203        1/1            assign intr_test_q [AON_WKUP] = reg2hw.intr_test.wkup_timer_expired.q;
           Tests:       T1 T2 T3 
204        1/1            assign intr_state_q[AON_WKUP] = reg2hw.intr_state.wkup_timer_expired.q;
           Tests:       T1 T2 T3 
205        1/1            assign intr_test_q [AON_WDOG] = reg2hw.intr_test.wdog_timer_bark.q;
           Tests:       T1 T2 T3 
206        1/1            assign intr_state_q[AON_WDOG] = reg2hw.intr_state.wdog_timer_bark.q;
           Tests:       T1 T2 T3 
207                     
208                       // Interrupts to registers
209        1/1            assign hw2reg.intr_state.wkup_timer_expired.d  = intr_state_d[AON_WKUP];
           Tests:       T1 T2 T3 
210        1/1            assign hw2reg.intr_state.wkup_timer_expired.de = intr_state_de;
           Tests:       T1 T2 T3 
211        1/1            assign hw2reg.intr_state.wdog_timer_bark.d  = intr_state_d[AON_WDOG];
           Tests:       T1 T2 T3 
212        1/1            assign hw2reg.intr_state.wdog_timer_bark.de = intr_state_de;
           Tests:       T1 T2 T3 
213                     
214                       prim_intr_hw #(
215                         .Width (2)
216                       ) u_intr_hw (
217                         .clk_i,
218                         .rst_ni,
219                         .event_intr_i           (intr_set),
220                         .reg2hw_intr_enable_q_i (2'b11),
221                         .reg2hw_intr_test_q_i   (intr_test_q),
222                         .reg2hw_intr_test_qe_i  (intr_test_qe),
223                         .reg2hw_intr_state_q_i  (intr_state_q),
224                         .hw2reg_intr_state_de_o (intr_state_de),
225                         .hw2reg_intr_state_d_o  (intr_state_d),
226                     
227                         .intr_o                 (intr_out)
228                       );
229                     
230        1/1            assign intr_wkup_timer_expired_o = intr_out[AON_WKUP];
           Tests:       T1 T2 T3 
231        1/1            assign intr_wdog_timer_bark_o = intr_out[AON_WDOG];
           Tests:       T1 T2 T3 
232                     
233                       // The interrupt line can be routed as nmi as well.
234        1/1            assign nmi_wdog_timer_bark_o = intr_wdog_timer_bark_o;
           Tests:       T1 T2 T3 
235                     
236                       ///////////////////
237                       // Reset Request //
238                       ///////////////////
239                     
240                       // Once set, the reset request remains asserted until the next aon reset
241        1/1            assign aon_rst_req_d = aon_rst_req_set | aon_rst_req_q;
           Tests:       T1 T6 T9 
242                     
243                       always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
244        1/1              if (!rst_aon_ni) begin
           Tests:       T1 T2 T3 
245        1/1                aon_rst_req_q <= 1'b0;
           Tests:       T1 T2 T3 
246                         end else begin
247        1/1                aon_rst_req_q <= aon_rst_req_d;
           Tests:       T1 T2 T3 
248                         end
249                       end
250                     
251        1/1            assign aon_timer_rst_req_o = aon_rst_req_q;
           Tests:       T6 T10 T13 

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	10	8	80.00
Logical	10	8	80.00
Non-Logical	0	0
Event	0	0

 LINE       109
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       165
 EXPRESSION (aon_wkup_intr_set | aon_wdog_intr_set)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T13
1	0	Covered	T2,T3,T4

 LINE       201
 EXPRESSION (reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe)
             -------------------1------------------   -----------------2-----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       241
 EXPRESSION (aon_rst_req_set | aon_rst_req_q)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T13
1	0	Covered	T6,T10,T13

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	35	35	100.00
Total Bits	356	356	100.00
Total Bits 0->1	178	178	100.00
Total Bits 1->0	178	178	100.00

Ports	35	35	100.00
Port Bits	356	356	100.00
Port Bits 0->1	178	178	100.00
Port Bits 1->0	178	178	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T11,T6,T12	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T11,T6,T12	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T11	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T11,T4	Yes	T2,T11,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T11,T4	Yes	T2,T11,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T11,T4	Yes	T2,T11,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T6,T13,T14	Yes	T6,T13,T14	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T6,T13	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T11,T12,T15	Yes	T11,T12,T15	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T11,T12,T15	Yes	T11,T12,T15	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T1,T5,T6	Yes	T16,T17,T18	INPUT
intr_wkup_timer_expired_o	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	OUTPUT
wkup_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T6,T13,T16	Yes	T6,T10,T13	OUTPUT
sleep_mode_i	Yes	Yes	T1,T2,T3	Yes	T17,T18,T19	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	244	2	2	100.00

244            if (!rst_aon_ni) begin
               -1-  
245              aon_rst_req_q <= 1'b0;
                 ==>
246            end else begin
247              aon_rst_req_q <= aon_rst_req_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	579185241	579046059	0	0
FpvSecCmRegWeOnehotCheck_A	579185241	70	0	0
IntrWdogKnown_A	579185241	579046059	0	0
IntrWkupKnown_A	579185241	579046059	0	0
RstReqKnown_A	2235752	2180436	0	0
TlOAReadyKnown_A	579185241	579046059	0	0
TlODValidKnown_A	579185241	579046059	0	0
WkupReqKnown_A	2235752	2180436	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	70	0	0
T4	14618	0	0	0
T5	97066	0	0	0
T6	249077	0	0	0
T7	10247	0	0	0
T8	430106	0	0	0
T9	23936	0	0	0
T10	9235	0	0	0
T11	90582	10	0	0
T12	170839	10	0	0
T13	431240	0	0	0
T15	0	10	0	0
T20	0	20	0	0
T21	0	20	0	0

IntrWdogKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

IntrWkupKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

RstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2235752	2180436	0	0
T1	116	29	0	0
T2	129	36	0	0
T3	4611	4555	0	0
T4	116	25	0	0
T5	238	152	0	0
T6	507	397	0	0
T7	81	19	0	0
T8	4778	4690	0	0
T11	861	12	0	0
T12	775	5	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579185241	579046059	0	0
T1	5283	5232	0	0
T2	7160	7081	0	0
T3	119915	119907	0	0
T4	14618	14525	0	0
T5	97066	96991	0	0
T6	249077	244120	0	0
T7	10247	10172	0	0
T8	430106	430048	0	0
T11	90582	89809	0	0
T12	170839	169959	0	0

WkupReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2235752	2180436	0	0
T1	116	29	0	0
T2	129	36	0	0
T3	4611	4555	0	0
T4	116	25	0	0
T5	238	152	0	0
T6	507	397	0	0
T7	81	19	0	0
T8	4778	4690	0	0
T11	861	12	0	0
T12	775	5	0	0