Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wkup_ctrl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wkup_thold_hi_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wkup_thold_lo_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.86 100.00 71.43 100.00 100.00 u_wkup_count_hi_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.21 100.00 92.86 100.00 100.00 u_wkup_count_lo_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wdog_ctrl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wdog_bark_thold_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wdog_bite_thold_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.21 100.00 92.86 100.00 100.00 u_wdog_count_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.44 100.00 93.75 100.00 100.00 u_wkup_cause_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2147483647 50050 0 0
SrcPulseCheck_M 2147483647 52826 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 50050 0 0
T1 27330 21 0 0
T2 73958 26 0 0
T3 123334 21 0 0
T4 207544 26 0 0
T5 143376 21 0 0
T6 245874 26 0 0
T7 252242 21 0 0
T8 310318 26 0 0
T9 2630132 25 0 0
T10 0 23 0 0
T11 1725518 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 52826 0 0
T1 44398 21 0 0
T2 122250 26 0 0
T3 204650 21 0 0
T4 345000 26 0 0
T5 237936 21 0 0
T6 408862 26 0 0
T7 419518 21 0 0
T8 516066 26 0 0
T9 4345132 25 0 0
T10 0 23 0 0
T11 2868514 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 4342 0 0
SrcPulseCheck_M 651951300 4684 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 4342 0 0
T1 108 2 0 0
T2 95 2 0 0
T3 85 2 0 0
T4 85 2 0 0
T5 96 2 0 0
T6 87 2 0 0
T7 83 2 0 0
T8 106 2 0 0
T9 3602 3 0 0
T10 0 2 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 4684 0 0
T1 4375 2 0 0
T2 12168 2 0 0
T3 20414 2 0 0
T4 34449 2 0 0
T5 23736 2 0 0
T6 40834 2 0 0
T7 41902 2 0 0
T8 51543 2 0 0
T9 432352 3 0 0
T10 0 2 0 0
T11 286438 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 651951300 4592 0 0
SrcPulseCheck_M 2367552 4594 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 4592 0 0
T1 4375 2 0 0
T2 12168 2 0 0
T3 20414 2 0 0
T4 34449 2 0 0
T5 23736 2 0 0
T6 40834 2 0 0
T7 41902 2 0 0
T8 51543 2 0 0
T9 432352 3 0 0
T10 0 2 0 0
T11 286438 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 4594 0 0
T1 108 2 0 0
T2 95 2 0 0
T3 85 2 0 0
T4 85 2 0 0
T5 96 2 0 0
T6 87 2 0 0
T7 83 2 0 0
T8 106 2 0 0
T9 3602 3 0 0
T10 0 2 0 0
T11 689 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT12,T17,T20
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 2433 0 0
SrcPulseCheck_M 651951300 2691 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 2433 0 0
T1 108 1 0 0
T2 95 1 0 0
T3 85 1 0 0
T4 85 1 0 0
T5 96 1 0 0
T6 87 1 0 0
T7 83 1 0 0
T8 106 1 0 0
T9 3602 1 0 0
T10 0 1 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 2691 0 0
T1 4375 1 0 0
T2 12168 1 0 0
T3 20414 1 0 0
T4 34449 1 0 0
T5 23736 1 0 0
T6 40834 1 0 0
T7 41902 1 0 0
T8 51543 1 0 0
T9 432352 1 0 0
T10 0 1 0 0
T11 286438 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT12,T17,T20
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 651951300 2657 0 0
SrcPulseCheck_M 2367552 2657 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 2657 0 0
T1 4375 1 0 0
T2 12168 1 0 0
T3 20414 1 0 0
T4 34449 1 0 0
T5 23736 1 0 0
T6 40834 1 0 0
T7 41902 1 0 0
T8 51543 1 0 0
T9 432352 1 0 0
T10 0 1 0 0
T11 286438 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 2657 0 0
T1 108 1 0 0
T2 95 1 0 0
T3 85 1 0 0
T4 85 1 0 0
T5 96 1 0 0
T6 87 1 0 0
T7 83 1 0 0
T8 106 1 0 0
T9 3602 1 0 0
T10 0 1 0 0
T11 689 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT12,T17,T20
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 2464 0 0
SrcPulseCheck_M 651951300 2719 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 2464 0 0
T1 108 1 0 0
T2 95 1 0 0
T3 85 1 0 0
T4 85 1 0 0
T5 96 1 0 0
T6 87 1 0 0
T7 83 1 0 0
T8 106 1 0 0
T9 3602 1 0 0
T10 0 1 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 2719 0 0
T1 4375 1 0 0
T2 12168 1 0 0
T3 20414 1 0 0
T4 34449 1 0 0
T5 23736 1 0 0
T6 40834 1 0 0
T7 41902 1 0 0
T8 51543 1 0 0
T9 432352 1 0 0
T10 0 1 0 0
T11 286438 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT12,T17,T20
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 651951300 2686 0 0
SrcPulseCheck_M 2367552 2686 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 2686 0 0
T1 4375 1 0 0
T2 12168 1 0 0
T3 20414 1 0 0
T4 34449 1 0 0
T5 23736 1 0 0
T6 40834 1 0 0
T7 41902 1 0 0
T8 51543 1 0 0
T9 432352 1 0 0
T10 0 1 0 0
T11 286438 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 2686 0 0
T1 108 1 0 0
T2 95 1 0 0
T3 85 1 0 0
T4 85 1 0 0
T5 96 1 0 0
T6 87 1 0 0
T7 83 1 0 0
T8 106 1 0 0
T9 3602 1 0 0
T10 0 1 0 0
T11 689 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 3942 0 0
SrcPulseCheck_M 651951300 4220 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 3942 0 0
T1 108 2 0 0
T2 95 3 0 0
T3 85 2 0 0
T4 85 3 0 0
T5 96 2 0 0
T6 87 3 0 0
T7 83 2 0 0
T8 106 3 0 0
T9 3602 2 0 0
T10 0 2 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 4220 0 0
T1 4375 2 0 0
T2 12168 3 0 0
T3 20414 2 0 0
T4 34449 3 0 0
T5 23736 2 0 0
T6 40834 3 0 0
T7 41902 2 0 0
T8 51543 3 0 0
T9 432352 2 0 0
T10 0 2 0 0
T11 286438 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 3983 0 0
SrcPulseCheck_M 651951300 4254 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 3983 0 0
T1 108 2 0 0
T2 95 3 0 0
T3 85 2 0 0
T4 85 3 0 0
T5 96 2 0 0
T6 87 3 0 0
T7 83 2 0 0
T8 106 3 0 0
T9 3602 2 0 0
T10 0 2 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 4254 0 0
T1 4375 2 0 0
T2 12168 3 0 0
T3 20414 2 0 0
T4 34449 3 0 0
T5 23736 2 0 0
T6 40834 3 0 0
T7 41902 2 0 0
T8 51543 3 0 0
T9 432352 2 0 0
T10 0 2 0 0
T11 286438 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T4,T6
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 3439 0 0
SrcPulseCheck_M 651951300 3738 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 3439 0 0
T1 108 1 0 0
T2 95 2 0 0
T3 85 1 0 0
T4 85 2 0 0
T5 96 1 0 0
T6 87 2 0 0
T7 83 1 0 0
T8 106 2 0 0
T9 3602 2 0 0
T10 0 2 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 3738 0 0
T1 4375 1 0 0
T2 12168 2 0 0
T3 20414 1 0 0
T4 34449 2 0 0
T5 23736 1 0 0
T6 40834 2 0 0
T7 41902 1 0 0
T8 51543 2 0 0
T9 432352 2 0 0
T10 0 2 0 0
T11 286438 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T4,T6
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 651951300 3656 0 0
SrcPulseCheck_M 2367552 3656 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 3656 0 0
T1 4375 1 0 0
T2 12168 2 0 0
T3 20414 1 0 0
T4 34449 2 0 0
T5 23736 1 0 0
T6 40834 2 0 0
T7 41902 1 0 0
T8 51543 2 0 0
T9 432352 2 0 0
T10 0 2 0 0
T11 286438 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 3656 0 0
T1 108 1 0 0
T2 95 2 0 0
T3 85 1 0 0
T4 85 2 0 0
T5 96 1 0 0
T6 87 2 0 0
T7 83 1 0 0
T8 106 2 0 0
T9 3602 2 0 0
T10 0 2 0 0
T11 689 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT12,T17,T20
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 2420 0 0
SrcPulseCheck_M 651951300 2688 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 2420 0 0
T1 108 1 0 0
T2 95 1 0 0
T3 85 1 0 0
T4 85 1 0 0
T5 96 1 0 0
T6 87 1 0 0
T7 83 1 0 0
T8 106 1 0 0
T9 3602 1 0 0
T10 0 1 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 2688 0 0
T1 4375 1 0 0
T2 12168 1 0 0
T3 20414 1 0 0
T4 34449 1 0 0
T5 23736 1 0 0
T6 40834 1 0 0
T7 41902 1 0 0
T8 51543 1 0 0
T9 432352 1 0 0
T10 0 1 0 0
T11 286438 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT12,T17,T20
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 651951300 2650 0 0
SrcPulseCheck_M 2367552 2650 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 2650 0 0
T1 4375 1 0 0
T2 12168 1 0 0
T3 20414 1 0 0
T4 34449 1 0 0
T5 23736 1 0 0
T6 40834 1 0 0
T7 41902 1 0 0
T8 51543 1 0 0
T9 432352 1 0 0
T10 0 1 0 0
T11 286438 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 2650 0 0
T1 108 1 0 0
T2 95 1 0 0
T3 85 1 0 0
T4 85 1 0 0
T5 96 1 0 0
T6 87 1 0 0
T7 83 1 0 0
T8 106 1 0 0
T9 3602 1 0 0
T10 0 1 0 0
T11 689 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT12,T17,T20
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 2432 0 0
SrcPulseCheck_M 651951300 2712 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 2432 0 0
T1 108 1 0 0
T2 95 1 0 0
T3 85 1 0 0
T4 85 1 0 0
T5 96 1 0 0
T6 87 1 0 0
T7 83 1 0 0
T8 106 1 0 0
T9 3602 1 0 0
T10 0 1 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 2712 0 0
T1 4375 1 0 0
T2 12168 1 0 0
T3 20414 1 0 0
T4 34449 1 0 0
T5 23736 1 0 0
T6 40834 1 0 0
T7 41902 1 0 0
T8 51543 1 0 0
T9 432352 1 0 0
T10 0 1 0 0
T11 286438 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT12,T17,T20
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 651951300 2673 0 0
SrcPulseCheck_M 2367552 2673 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 2673 0 0
T1 4375 1 0 0
T2 12168 1 0 0
T3 20414 1 0 0
T4 34449 1 0 0
T5 23736 1 0 0
T6 40834 1 0 0
T7 41902 1 0 0
T8 51543 1 0 0
T9 432352 1 0 0
T10 0 1 0 0
T11 286438 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 2673 0 0
T1 108 1 0 0
T2 95 1 0 0
T3 85 1 0 0
T4 85 1 0 0
T5 96 1 0 0
T6 87 1 0 0
T7 83 1 0 0
T8 106 1 0 0
T9 3602 1 0 0
T10 0 1 0 0
T11 689 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 3939 0 0
SrcPulseCheck_M 651951300 4233 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 3939 0 0
T1 108 2 0 0
T2 95 3 0 0
T3 85 2 0 0
T4 85 3 0 0
T5 96 2 0 0
T6 87 3 0 0
T7 83 2 0 0
T8 106 3 0 0
T9 3602 2 0 0
T10 0 2 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 4233 0 0
T1 4375 2 0 0
T2 12168 3 0 0
T3 20414 2 0 0
T4 34449 3 0 0
T5 23736 2 0 0
T6 40834 3 0 0
T7 41902 2 0 0
T8 51543 3 0 0
T9 432352 2 0 0
T10 0 2 0 0
T11 286438 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T3  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T17,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT12,T17,T20
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2367552 1742 0 0
SrcPulseCheck_M 651951300 1971 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2367552 1742 0 0
T1 108 1 0 0
T2 95 1 0 0
T3 85 1 0 0
T4 85 1 0 0
T5 96 1 0 0
T6 87 1 0 0
T7 83 1 0 0
T8 106 1 0 0
T9 3602 1 0 0
T10 0 1 0 0
T11 689 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 651951300 1971 0 0
T1 4375 1 0 0
T2 12168 1 0 0
T3 20414 1 0 0
T4 34449 1 0 0
T5 23736 1 0 0
T6 40834 1 0 0
T7 41902 1 0 0
T8 51543 1 0 0
T9 432352 1 0 0
T10 0 1 0 0
T11 286438 0 0 0