Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	380608	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4643251	1		T1	12		T2	16		T3	13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1236657	1		T1	1		T2	1		T3	1
values[0x0]	1773800	1		T1	8		T2	12		T3	8
values[0x1]	2013402	1		T1	9		T2	9		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	169417	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4854442	1		T1	13		T2	18		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17968	1		T9	1		T16	2		T58	3
valid_sources[0x01]	22370	1		T17	3		T18	1		T217	1
valid_sources[0x02]	20549	1		T9	2		T28	1		T17	1
valid_sources[0x03]	19799	1		T10	4		T17	2		T21	210
valid_sources[0x04]	19447	1		T60	20		T21	171		T34	2
valid_sources[0x05]	19423	1		T9	1		T17	3		T21	147
valid_sources[0x06]	17525	1		T194	1		T17	1		T21	165
valid_sources[0x07]	19059	1		T9	1		T17	1		T18	1
valid_sources[0x08]	17656	1		T9	1		T25	1		T59	1
valid_sources[0x09]	20651	1		T5	2		T41	1		T194	1
valid_sources[0x0a]	20239	1		T9	1		T58	1		T17	2
valid_sources[0x0b]	18864	1		T9	2		T17	2		T18	1
valid_sources[0x0c]	18297	1		T17	3		T32	1		T21	117
valid_sources[0x0d]	20266	1		T9	1		T14	1		T17	4
valid_sources[0x0e]	18883	1		T3	1		T5	2		T58	1
valid_sources[0x0f]	20010	1		T9	4		T21	155		T35	1
valid_sources[0x10]	21220	1		T194	1		T17	3		T18	3
valid_sources[0x11]	19861	1		T9	1		T17	1		T18	2
valid_sources[0x12]	19807	1		T9	1		T16	1		T17	2
valid_sources[0x13]	18759	1		T218	5		T17	1		T18	3
valid_sources[0x14]	21406	1		T1	2		T3	2		T204	1
valid_sources[0x15]	20786	1		T9	1		T28	1		T17	5
valid_sources[0x16]	19465	1		T17	3		T18	1		T21	188
valid_sources[0x17]	19575	1		T9	1		T21	163		T34	1
valid_sources[0x18]	20328	1		T9	4		T21	133		T34	2
valid_sources[0x19]	18156	1		T2	1		T4	6		T9	4
valid_sources[0x1a]	19695	1		T9	1		T18	1		T21	142
valid_sources[0x1b]	17979	1		T8	1		T9	1		T194	1
valid_sources[0x1c]	18993	1		T218	6		T18	1		T21	139
valid_sources[0x1d]	19813	1		T9	3		T28	1		T25	2
valid_sources[0x1e]	19937	1		T17	4		T18	2		T21	150
valid_sources[0x1f]	20242	1		T9	2		T219	1		T17	1
valid_sources[0x20]	18492	1		T9	1		T29	1		T18	4
valid_sources[0x21]	19841	1		T219	1		T17	1		T18	4
valid_sources[0x22]	19132	1		T28	1		T18	1		T21	144
valid_sources[0x23]	19317	1		T9	2		T21	169		T35	2
valid_sources[0x24]	18424	1		T18	2		T21	139		T34	8
valid_sources[0x25]	19581	1		T14	1		T21	152		T35	2
valid_sources[0x26]	20525	1		T9	3		T14	1		T58	4
valid_sources[0x27]	21007	1		T9	6		T13	1		T18	3
valid_sources[0x28]	21407	1		T9	2		T17	1		T32	4
valid_sources[0x29]	20120	1		T2	1		T9	3		T17	1
valid_sources[0x2a]	19666	1		T28	1		T17	1		T18	2
valid_sources[0x2b]	19766	1		T9	1		T18	1		T21	117
valid_sources[0x2c]	18019	1		T9	3		T41	1		T17	1
valid_sources[0x2d]	19883	1		T4	1		T9	1		T17	2
valid_sources[0x2e]	18847	1		T1	4		T17	1		T21	142
valid_sources[0x2f]	20137	1		T3	1		T41	1		T18	3
valid_sources[0x30]	20877	1		T3	1		T13	2		T58	1
valid_sources[0x31]	19458	1		T9	5		T12	8		T17	6
valid_sources[0x32]	18314	1		T9	3		T17	2		T21	137
valid_sources[0x33]	19373	1		T9	2		T28	1		T21	150
valid_sources[0x34]	18754	1		T9	1		T14	1		T41	1
valid_sources[0x35]	19897	1		T9	2		T17	1		T21	132
valid_sources[0x36]	19572	1		T9	1		T41	1		T17	2
valid_sources[0x37]	22582	1		T9	2		T17	3		T18	1
valid_sources[0x38]	18654	1		T9	1		T18	1		T21	140
valid_sources[0x39]	18977	1		T9	1		T220	1		T18	3
valid_sources[0x3a]	19758	1		T9	1		T14	1		T29	1
valid_sources[0x3b]	18041	1		T4	2		T9	1		T17	2
valid_sources[0x3c]	18244	1		T9	1		T17	1		T18	2
valid_sources[0x3d]	19506	1		T7	18		T9	1		T41	3
valid_sources[0x3e]	20534	1		T17	1		T18	4		T21	164
valid_sources[0x3f]	20295	1		T9	2		T28	1		T18	2
valid_sources[0x40]	19991	1		T9	2		T17	1		T18	3
valid_sources[0x41]	19601	1		T9	3		T14	1		T21	157
valid_sources[0x42]	18358	1		T9	3		T28	1		T17	1
valid_sources[0x43]	20217	1		T9	2		T16	2		T59	1
valid_sources[0x44]	19138	1		T9	1		T18	1		T21	163
valid_sources[0x45]	20297	1		T9	2		T41	1		T59	4
valid_sources[0x46]	19641	1		T17	2		T18	2		T21	143
valid_sources[0x47]	18757	1		T9	2		T10	7		T17	1
valid_sources[0x48]	19129	1		T9	1		T218	1		T17	1
valid_sources[0x49]	19341	1		T14	1		T58	1		T17	1
valid_sources[0x4a]	18451	1		T25	2		T17	2		T18	5
valid_sources[0x4b]	18906	1		T17	1		T18	1		T21	151
valid_sources[0x4c]	18472	1		T9	1		T18	1		T21	132
valid_sources[0x4d]	19278	1		T9	3		T194	1		T17	1
valid_sources[0x4e]	20079	1		T17	1		T18	2		T21	126
valid_sources[0x4f]	20652	1		T9	1		T21	170		T35	2
valid_sources[0x50]	20128	1		T2	1		T28	1		T41	1
valid_sources[0x51]	17768	1		T9	2		T17	2		T18	2
valid_sources[0x52]	20422	1		T9	1		T21	156		T35	2
valid_sources[0x53]	19576	1		T9	1		T17	2		T18	1
valid_sources[0x54]	19599	1		T9	1		T58	1		T19	19
valid_sources[0x55]	19772	1		T9	1		T21	212		T34	2
valid_sources[0x56]	19310	1		T12	3		T13	3		T18	6
valid_sources[0x57]	19812	1		T8	1		T14	1		T17	4
valid_sources[0x58]	19511	1		T13	2		T25	3		T17	3
valid_sources[0x59]	20592	1		T3	1		T17	2		T18	2
valid_sources[0x5a]	19581	1		T2	1		T9	1		T28	1
valid_sources[0x5b]	20049	1		T8	1		T25	1		T17	1
valid_sources[0x5c]	20604	1		T9	1		T17	2		T18	2
valid_sources[0x5d]	20139	1		T9	1		T17	2		T18	3
valid_sources[0x5e]	19115	1		T2	2		T9	1		T25	4
valid_sources[0x5f]	20445	1		T2	2		T9	3		T21	145
valid_sources[0x60]	21147	1		T5	3		T9	2		T18	4
valid_sources[0x61]	21011	1		T17	1		T18	4		T32	1
valid_sources[0x62]	19281	1		T9	2		T16	1		T17	1
valid_sources[0x63]	18467	1		T3	1		T28	1		T17	1
valid_sources[0x64]	17622	1		T17	1		T217	1		T21	141
valid_sources[0x65]	20082	1		T9	2		T204	3		T17	1
valid_sources[0x66]	18962	1		T5	3		T29	2		T194	1
valid_sources[0x67]	18001	1		T9	4		T17	1		T18	3
valid_sources[0x68]	19089	1		T9	4		T13	3		T218	1
valid_sources[0x69]	18362	1		T17	5		T18	5		T21	136
valid_sources[0x6a]	20366	1		T8	1		T9	2		T17	1
valid_sources[0x6b]	18233	1		T9	1		T14	1		T219	1
valid_sources[0x6c]	20035	1		T8	1		T9	1		T21	127
valid_sources[0x6d]	18432	1		T9	2		T17	2		T32	1
valid_sources[0x6e]	18490	1		T17	1		T18	3		T21	109
valid_sources[0x6f]	19461	1		T17	1		T18	1		T21	128
valid_sources[0x70]	20560	1		T9	2		T17	2		T18	2
valid_sources[0x71]	19491	1		T9	1		T14	1		T219	1
valid_sources[0x72]	19891	1		T17	2		T18	2		T221	4
valid_sources[0x73]	18646	1		T9	4		T25	1		T21	167
valid_sources[0x74]	19741	1		T17	4		T21	126		T22	136
valid_sources[0x75]	21251	1		T17	1		T21	151		T34	2
valid_sources[0x76]	19069	1		T9	1		T32	1		T21	142
valid_sources[0x77]	19993	1		T3	1		T16	1		T18	2
valid_sources[0x78]	20614	1		T2	1		T9	1		T194	1
valid_sources[0x79]	20508	1		T17	2		T18	2		T21	184
valid_sources[0x7a]	19821	1		T9	2		T17	2		T21	181
valid_sources[0x7b]	18726	1		T21	149		T35	2		T22	105
valid_sources[0x7c]	19399	1		T6	8		T9	2		T17	6
valid_sources[0x7d]	18875	1		T9	1		T204	1		T17	1
valid_sources[0x7e]	18196	1		T14	1		T17	3		T18	2
valid_sources[0x7f]	19279	1		T4	8		T16	3		T17	1
valid_sources[0x80]	19693	1		T9	2		T18	1		T21	151

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1159784

1

T4

1

T5

1

T6

1

values[0x0]

all_enables

biggest_size

1742163

1

T1

7

T2

9

T3

7

values[0x1]

all_enables

biggest_size

1741304

1

T1

5

T2

7

T3

6