Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41692	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

319737

1

T1

253

T2

12

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	91683	1			T1	43		T2	1		T3	1
values[0x0]	128029	1			T1	158		T2	5		T3	4
values[0x1]	141717	1			T1	154		T2	12		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25356	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

336073

1

T1

267

T2

13

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1730	1			T21	1		T17	13		T20	29
valid_sources[0x01]	1234	1			T4	3		T17	19		T20	28
valid_sources[0x02]	1013	1			T17	16		T20	13		T23	18
valid_sources[0x03]	1278	1			T17	25		T20	14		T23	20
valid_sources[0x04]	1521	1			T13	1		T16	20		T17	26
valid_sources[0x05]	1675	1			T17	22		T20	19		T23	21
valid_sources[0x06]	1499	1			T17	21		T20	19		T23	16
valid_sources[0x07]	1561	1			T21	1		T17	17		T20	2
valid_sources[0x08]	1355	1			T4	4		T14	1		T17	16
valid_sources[0x09]	1326	1			T15	4		T17	15		T20	11
valid_sources[0x0a]	1157	1			T17	23		T20	23		T23	19
valid_sources[0x0b]	1165	1			T17	12		T20	14		T23	12
valid_sources[0x0c]	1271	1			T17	24		T20	17		T23	22
valid_sources[0x0d]	1189	1			T3	1		T17	9		T20	12
valid_sources[0x0e]	1600	1			T17	7		T20	31		T23	20
valid_sources[0x0f]	1220	1			T7	2		T17	12		T20	3
valid_sources[0x10]	1501	1			T2	1		T10	1		T17	20
valid_sources[0x11]	1446	1			T2	1		T17	19		T20	19
valid_sources[0x12]	2018	1			T17	15		T20	23		T23	20
valid_sources[0x13]	1501	1			T2	1		T17	27		T20	11
valid_sources[0x14]	1377	1			T17	19		T20	21		T23	12
valid_sources[0x15]	1661	1			T17	20		T20	4		T23	19
valid_sources[0x16]	1108	1			T17	18		T20	32		T23	21
valid_sources[0x17]	2111	1			T13	1		T17	21		T20	22
valid_sources[0x18]	1082	1			T3	1		T17	24		T20	9
valid_sources[0x19]	1554	1			T17	13		T20	23		T23	17
valid_sources[0x1a]	1745	1			T17	9		T20	53		T23	19
valid_sources[0x1b]	1819	1			T14	2		T22	1		T17	17
valid_sources[0x1c]	1364	1			T17	9		T20	14		T23	17
valid_sources[0x1d]	1436	1			T17	13		T20	16		T23	22
valid_sources[0x1e]	1606	1			T5	1		T17	7		T20	21
valid_sources[0x1f]	1263	1			T5	1		T15	2		T17	22
valid_sources[0x20]	1059	1			T17	8		T20	5		T23	17
valid_sources[0x21]	1351	1			T17	16		T20	3		T23	15
valid_sources[0x22]	1845	1			T17	13		T20	6		T23	17
valid_sources[0x23]	1576	1			T17	20		T20	11		T23	11
valid_sources[0x24]	1116	1			T2	1		T5	1		T17	13
valid_sources[0x25]	1247	1			T3	2		T17	13		T19	22
valid_sources[0x26]	1727	1			T17	15		T20	20		T23	26
valid_sources[0x27]	1517	1			T5	1		T17	6		T20	21
valid_sources[0x28]	1126	1			T17	16		T20	22		T23	14
valid_sources[0x29]	1362	1			T17	14		T20	57		T23	14
valid_sources[0x2a]	1659	1			T17	20		T20	2		T23	27
valid_sources[0x2b]	1305	1			T15	3		T17	17		T20	22
valid_sources[0x2c]	1220	1			T17	10		T20	30		T23	20
valid_sources[0x2d]	1614	1			T17	15		T20	37		T23	19
valid_sources[0x2e]	1614	1			T10	1		T17	16		T20	8
valid_sources[0x2f]	2179	1			T17	11		T20	9		T23	14
valid_sources[0x30]	1053	1			T17	18		T20	17		T23	17
valid_sources[0x31]	1163	1			T17	12		T20	27		T23	20
valid_sources[0x32]	1209	1			T22	3		T17	11		T20	9
valid_sources[0x33]	1496	1			T13	1		T17	13		T20	25
valid_sources[0x34]	1259	1			T2	1		T17	22		T20	13
valid_sources[0x35]	1669	1			T2	1		T17	9		T20	28
valid_sources[0x36]	1002	1			T22	2		T17	25		T20	25
valid_sources[0x37]	1339	1			T17	15		T20	4		T23	18
valid_sources[0x38]	1473	1			T17	12		T20	19		T23	13
valid_sources[0x39]	1650	1			T17	16		T20	9		T23	16
valid_sources[0x3a]	1351	1			T17	12		T20	19		T23	14
valid_sources[0x3b]	1533	1			T22	1		T17	16		T20	12
valid_sources[0x3c]	1328	1			T17	25		T20	20		T23	19
valid_sources[0x3d]	1344	1			T13	1		T17	10		T20	29
valid_sources[0x3e]	1657	1			T17	15		T20	16		T23	14
valid_sources[0x3f]	1534	1			T21	1		T17	11		T20	8
valid_sources[0x40]	1241	1			T17	19		T20	6		T23	16
valid_sources[0x41]	996	1			T17	11		T20	12		T23	18
valid_sources[0x42]	1447	1			T17	23		T20	8		T23	20
valid_sources[0x43]	1375	1			T10	1		T17	15		T20	21
valid_sources[0x44]	1252	1			T17	12		T20	27		T23	11
valid_sources[0x45]	1256	1			T17	8		T20	5		T23	20
valid_sources[0x46]	1651	1			T17	14		T20	5		T23	20
valid_sources[0x47]	1370	1			T7	6		T17	9		T20	31
valid_sources[0x48]	1616	1			T22	1		T17	18		T20	17
valid_sources[0x49]	1297	1			T17	19		T20	5		T23	21
valid_sources[0x4a]	1284	1			T17	11		T20	14		T23	13
valid_sources[0x4b]	1407	1			T3	3		T17	21		T20	12
valid_sources[0x4c]	1205	1			T17	7		T20	6		T23	27
valid_sources[0x4d]	1064	1			T17	5		T20	54		T23	13
valid_sources[0x4e]	1074	1			T17	12		T20	28		T23	23
valid_sources[0x4f]	2117	1			T17	13		T20	18		T23	15
valid_sources[0x50]	1918	1			T17	12		T20	2		T23	28
valid_sources[0x51]	1252	1			T17	12		T20	26		T23	19
valid_sources[0x52]	1503	1			T17	12		T20	10		T23	18
valid_sources[0x53]	2224	1			T2	2		T17	15		T20	29
valid_sources[0x54]	1412	1			T17	19		T20	16		T23	15
valid_sources[0x55]	1416	1			T17	13		T20	29		T23	24
valid_sources[0x56]	1203	1			T17	19		T20	44		T23	14
valid_sources[0x57]	1636	1			T2	1		T17	13		T20	21
valid_sources[0x58]	1166	1			T4	2		T5	1		T17	22
valid_sources[0x59]	1231	1			T22	2		T17	9		T20	26
valid_sources[0x5a]	1804	1			T6	22		T17	12		T20	31
valid_sources[0x5b]	1410	1			T9	4		T17	7		T20	25
valid_sources[0x5c]	1278	1			T17	13		T20	25		T23	21
valid_sources[0x5d]	1044	1			T10	1		T17	11		T20	38
valid_sources[0x5e]	1621	1			T13	1		T17	17		T20	21
valid_sources[0x5f]	1931	1			T2	1		T13	2		T17	11
valid_sources[0x60]	1129	1			T2	1		T7	3		T17	18
valid_sources[0x61]	1409	1			T17	11		T20	40		T23	16
valid_sources[0x62]	1434	1			T17	13		T20	19		T23	21
valid_sources[0x63]	1292	1			T15	4		T17	17		T20	19
valid_sources[0x64]	1349	1			T17	6		T20	4		T23	20
valid_sources[0x65]	1747	1			T4	1		T17	22		T20	16
valid_sources[0x66]	1316	1			T17	12		T20	27		T23	24
valid_sources[0x67]	1534	1			T2	1		T17	13		T20	26
valid_sources[0x68]	1287	1			T5	1		T21	1		T17	21
valid_sources[0x69]	1729	1			T14	8		T17	10		T20	11
valid_sources[0x6a]	1626	1			T2	1		T17	20		T20	4
valid_sources[0x6b]	1581	1			T7	1		T22	1		T17	22
valid_sources[0x6c]	1214	1			T17	13		T20	17		T23	22
valid_sources[0x6d]	1246	1			T17	10		T20	12		T23	23
valid_sources[0x6e]	1936	1			T17	9		T20	7		T23	22
valid_sources[0x6f]	1506	1			T17	11		T20	25		T23	19
valid_sources[0x70]	931	1			T17	15		T20	25		T23	21
valid_sources[0x71]	1507	1			T5	1		T8	20		T21	1
valid_sources[0x72]	1246	1			T10	6		T17	23		T20	20
valid_sources[0x73]	1249	1			T17	8		T20	10		T23	15
valid_sources[0x74]	1560	1			T17	17		T20	11		T23	18
valid_sources[0x75]	1393	1			T17	23		T20	18		T23	17
valid_sources[0x76]	1703	1			T17	10		T20	38		T23	20
valid_sources[0x77]	1483	1			T17	21		T20	12		T23	22
valid_sources[0x78]	1480	1			T17	18		T20	43		T23	22
valid_sources[0x79]	1577	1			T17	12		T20	29		T23	13
valid_sources[0x7a]	1614	1			T3	1		T17	13		T20	42
valid_sources[0x7b]	1609	1			T10	4		T17	20		T20	3
valid_sources[0x7c]	1415	1			T17	16		T20	19		T23	25
valid_sources[0x7d]	1157	1			T17	16		T20	13		T23	18
valid_sources[0x7e]	1255	1			T5	2		T17	25		T20	23
valid_sources[0x7f]	1171	1			T21	1		T17	19		T20	12
valid_sources[0x80]	1235	1			T2	3		T9	2		T17	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79450

1

T1

20

T3

1

T4

1

values[0x0]

all_enables

biggest_size

120604

1

T1

113

T2

5

T3

3

values[0x1]

all_enables

biggest_size

119683

1

T1

120

T2

7

T3

9