Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	562854773	314924	0	0
wdog_bark_thold_rd_A	562854773	6823	0	0
wdog_bite_thold_rd_A	562854773	6180	0	0
wdog_ctrl_rd_A	562854773	6120	0	0
wdog_regwen_rd_A	562854773	7486	0	0
wkup_ctrl_rd_A	562854773	6234	0	0
wkup_thold_hi_rd_A	562854773	6962	0	0
wkup_thold_lo_rd_A	562854773	5827	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562854773	314924	0	0
T17	204703	3656	0	0
T18	12678	0	0	0
T19	11953	0	0	0
T20	228893	3926	0	0
T23	312457	5103	0	0
T29	11441	0	0	0
T30	14342	0	0	0
T31	5508	0	0	0
T32	0	4844	0	0
T33	0	475	0	0
T34	0	9919	0	0
T44	0	12203	0	0
T45	0	9203	0	0
T46	0	2177	0	0
T47	0	9487	0	0
T48	107961	0	0	0
T49	114344	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562854773	6823	0	0
T17	204703	462	0	0
T18	12678	0	0	0
T19	11953	0	0	0
T20	228893	0	0	0
T23	312457	0	0	0
T29	11441	0	0	0
T30	14342	0	0	0
T31	5508	0	0	0
T32	0	664	0	0
T33	0	90	0	0
T45	0	499	0	0
T48	107961	0	0	0
T49	114344	0	0	0
T78	0	327	0	0
T79	0	671	0	0
T80	0	41	0	0
T81	0	400	0	0
T82	0	184	0	0
T83	0	344	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562854773	6180	0	0
T17	204703	377	0	0
T18	12678	0	0	0
T19	11953	0	0	0
T20	228893	0	0	0
T23	312457	0	0	0
T29	11441	0	0	0
T30	14342	0	0	0
T31	5508	0	0	0
T32	0	568	0	0
T33	0	76	0	0
T45	0	526	0	0
T48	107961	0	0	0
T49	114344	0	0	0
T78	0	287	0	0
T79	0	561	0	0
T80	0	65	0	0
T81	0	340	0	0
T82	0	169	0	0
T83	0	308	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562854773	6120	0	0
T17	204703	368	0	0
T18	12678	0	0	0
T19	11953	0	0	0
T20	228893	0	0	0
T23	312457	0	0	0
T29	11441	0	0	0
T30	14342	0	0	0
T31	5508	0	0	0
T32	0	524	0	0
T33	0	81	0	0
T45	0	473	0	0
T48	107961	0	0	0
T49	114344	0	0	0
T78	0	283	0	0
T79	0	575	0	0
T80	0	84	0	0
T81	0	280	0	0
T82	0	171	0	0
T83	0	368	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562854773	7486	0	0
T17	204703	409	0	0
T18	12678	0	0	0
T19	11953	0	0	0
T20	228893	0	0	0
T23	312457	0	0	0
T29	11441	0	0	0
T30	14342	0	0	0
T31	5508	0	0	0
T32	0	578	0	0
T33	0	101	0	0
T45	0	601	0	0
T48	107961	0	0	0
T49	114344	0	0	0
T78	0	377	0	0
T79	0	692	0	0
T80	0	47	0	0
T81	0	343	0	0
T82	0	174	0	0
T83	0	351	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562854773	6234	0	0
T17	204703	358	0	0
T18	12678	0	0	0
T19	11953	0	0	0
T20	228893	0	0	0
T23	312457	0	0	0
T29	11441	0	0	0
T30	14342	0	0	0
T31	5508	0	0	0
T32	0	651	0	0
T33	0	110	0	0
T45	0	467	0	0
T48	107961	0	0	0
T49	114344	0	0	0
T78	0	201	0	0
T79	0	653	0	0
T80	0	62	0	0
T81	0	355	0	0
T82	0	152	0	0
T83	0	316	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562854773	6962	0	0
T17	204703	411	0	0
T18	12678	0	0	0
T19	11953	0	0	0
T20	228893	0	0	0
T23	312457	0	0	0
T29	11441	0	0	0
T30	14342	0	0	0
T31	5508	0	0	0
T32	0	597	0	0
T33	0	90	0	0
T45	0	658	0	0
T48	107961	0	0	0
T49	114344	0	0	0
T78	0	311	0	0
T79	0	772	0	0
T80	0	88	0	0
T81	0	326	0	0
T82	0	187	0	0
T83	0	426	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562854773	5827	0	0
T17	204703	313	0	0
T18	12678	0	0	0
T19	11953	0	0	0
T20	228893	0	0	0
T23	312457	0	0	0
T29	11441	0	0	0
T30	14342	0	0	0
T31	5508	0	0	0
T32	0	476	0	0
T33	0	114	0	0
T45	0	568	0	0
T48	107961	0	0	0
T49	114344	0	0	0
T78	0	267	0	0
T79	0	535	0	0
T80	0	63	0	0
T81	0	334	0	0
T82	0	145	0	0
T83	0	369	0	0