Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	812013473	5519907	0	0
wdog_bark_thold_rd_A	812013473	111713	0	0
wdog_bite_thold_rd_A	812013473	98447	0	0
wdog_ctrl_rd_A	812013473	97350	0	0
wdog_regwen_rd_A	812013473	112087	0	0
wkup_ctrl_rd_A	812013473	97459	0	0
wkup_thold_hi_rd_A	812013473	111389	0	0
wkup_thold_lo_rd_A	812013473	95210	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812013473	5519907	0	0
T21	172024	45312	0	0
T22	0	30092	0	0
T23	0	99860	0	0
T33	23749	0	0	0
T35	868675	0	0	0
T44	0	102749	0	0
T45	0	77357	0	0
T46	0	65533	0	0
T47	0	71297	0	0
T48	0	130520	0	0
T49	0	128485	0	0
T50	0	119435	0	0
T51	38006	0	0	0
T52	667008	0	0	0
T53	36827	0	0	0
T54	222606	0	0	0
T55	3944	0	0	0
T56	518815	0	0	0
T57	12319	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812013473	111713	0	0
T44	451016	10836	0	0
T45	298487	0	0	0
T46	266164	0	0	0
T49	0	12753	0	0
T82	0	18426	0	0
T96	0	5473	0	0
T97	0	13177	0	0
T98	0	4692	0	0
T99	0	9982	0	0
T100	0	10331	0	0
T101	0	8516	0	0
T102	0	4761	0	0
T103	9517	0	0	0
T104	352966	0	0	0
T105	48228	0	0	0
T106	18330	0	0	0
T107	17239	0	0	0
T108	639847	0	0	0
T109	3385	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812013473	98447	0	0
T44	451016	9332	0	0
T45	298487	0	0	0
T46	266164	0	0	0
T49	0	11138	0	0
T82	0	16269	0	0
T96	0	5133	0	0
T97	0	11410	0	0
T98	0	4230	0	0
T99	0	8622	0	0
T100	0	9218	0	0
T101	0	7044	0	0
T102	0	4249	0	0
T103	9517	0	0	0
T104	352966	0	0	0
T105	48228	0	0	0
T106	18330	0	0	0
T107	17239	0	0	0
T108	639847	0	0	0
T109	3385	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812013473	97350	0	0
T44	451016	9328	0	0
T45	298487	0	0	0
T46	266164	0	0	0
T49	0	10786	0	0
T82	0	15738	0	0
T96	0	4575	0	0
T97	0	11100	0	0
T98	0	4502	0	0
T99	0	8958	0	0
T100	0	9126	0	0
T101	0	7063	0	0
T102	0	4064	0	0
T103	9517	0	0	0
T104	352966	0	0	0
T105	48228	0	0	0
T106	18330	0	0	0
T107	17239	0	0	0
T108	639847	0	0	0
T109	3385	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812013473	112087	0	0
T44	451016	10619	0	0
T45	298487	0	0	0
T46	266164	0	0	0
T49	0	12543	0	0
T82	0	18079	0	0
T96	0	5528	0	0
T97	0	12702	0	0
T98	0	4749	0	0
T99	0	10600	0	0
T100	0	10586	0	0
T101	0	8264	0	0
T102	0	4876	0	0
T103	9517	0	0	0
T104	352966	0	0	0
T105	48228	0	0	0
T106	18330	0	0	0
T107	17239	0	0	0
T108	639847	0	0	0
T109	3385	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812013473	97459	0	0
T44	451016	8963	0	0
T45	298487	0	0	0
T46	266164	0	0	0
T49	0	11047	0	0
T82	0	16087	0	0
T96	0	4986	0	0
T97	0	11247	0	0
T98	0	4313	0	0
T99	0	8865	0	0
T100	0	8995	0	0
T101	0	7204	0	0
T102	0	3958	0	0
T103	9517	0	0	0
T104	352966	0	0	0
T105	48228	0	0	0
T106	18330	0	0	0
T107	17239	0	0	0
T108	639847	0	0	0
T109	3385	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812013473	111389	0	0
T44	451016	10718	0	0
T45	298487	0	0	0
T46	266164	0	0	0
T49	0	12407	0	0
T82	0	18269	0	0
T96	0	5680	0	0
T97	0	12620	0	0
T98	0	4664	0	0
T99	0	10312	0	0
T100	0	10849	0	0
T101	0	8010	0	0
T102	0	4488	0	0
T103	9517	0	0	0
T104	352966	0	0	0
T105	48228	0	0	0
T106	18330	0	0	0
T107	17239	0	0	0
T108	639847	0	0	0
T109	3385	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812013473	95210	0	0
T44	451016	8996	0	0
T45	298487	0	0	0
T46	266164	0	0	0
T49	0	10736	0	0
T82	0	15485	0	0
T96	0	4844	0	0
T97	0	11286	0	0
T98	0	3962	0	0
T99	0	8735	0	0
T100	0	8864	0	0
T101	0	6798	0	0
T102	0	3913	0	0
T103	9517	0	0	0
T104	352966	0	0	0
T105	48228	0	0	0
T106	18330	0	0	0
T107	17239	0	0	0
T108	639847	0	0	0
T109	3385	0	0	0