CLKMGR Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: 3df77bec1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.360s	232.198us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.880s	35.645us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.910s	60.753us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	11.200s	1.835ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	3.600s	954.501us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.680s	33.244us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.910s	60.753us	20	20	100.00
		clkmgr_csr_aliasing	3.600s	954.501us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	0.930s	98.438us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.830s	335.657us	50	50	100.00
V2	extclk	clkmgr_extclk	1.390s	202.264us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.050s	157.372us	50	50	100.00
V2	jitter	clkmgr_smoke	1.360s	232.198us	50	50	100.00
V2	frequency	clkmgr_frequency	15.990s	2.235ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.550s	2.414ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	15.990s	2.235ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.010m	16.450ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.910s	143.332us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.210s	177.556us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.000s	1.075ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.000s	1.075ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.880s	35.645us	5	5	100.00
		clkmgr_csr_rw	0.910s	60.753us	20	20	100.00
		clkmgr_csr_aliasing	3.600s	954.501us	5	5	100.00
		clkmgr_same_csr_outstanding	1.940s	366.628us	19	20	95.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.880s	35.645us	5	5	100.00
		clkmgr_csr_rw	0.910s	60.753us	20	20	100.00
		clkmgr_csr_aliasing	3.600s	954.501us	5	5	100.00
		clkmgr_same_csr_outstanding	1.940s	366.628us	19	20	95.00
V2		TOTAL			489	490	99.80
V2S	tl_intg_err	clkmgr_sec_cm	5.320s	1.231ms	5	5	100.00
		clkmgr_tl_intg_err	4.770s	947.698us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.910s	1.039ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.910s	1.039ms	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.910s	1.039ms	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.910s	1.039ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.930s	229.333us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.770s	947.698us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	15.990s	2.235ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.550s	2.414ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.910s	1.039ms	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.040s	428.677us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.100s	120.265us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.140s	160.462us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.180s	121.472us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.510s	285.801us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.910s	60.753us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.320s	1.231ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.910s	60.753us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.910s	60.753us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.320s	1.231ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	33.258m	435.888ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			958	960	99.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.61	99.12	95.28	100.00	100.00	98.71	96.97	93.18

Failure Buckets

• Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 1 failures:

  • Test clkmgr_same_csr_outstanding has 1 failures.

    • 2.clkmgr_same_csr_outstanding.1888284114
      Line 217, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @   6740089 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @   6740089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (clkmgr_frequency_vseq.sv:206) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 1 failures:

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 4.clkmgr_stress_all_with_rand_reset.72462980
      Line 1951, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 78269538215 ps: (clkmgr_frequency_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 78269538215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.16_19.12.30
• 2023.05.15_18.30.36
• 2023.05.14_17.56.25
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